AK5556VN_16 Datasheet, PDF (26/69 Pages) Asahi Kasei Microsystems – 6-Channel Differential 32-bit ADC

■ Timing Diagram
[1] PCM Mode
MCLK
LRCK
BICK
MCLK
LRCK
BICK
[AK5556]
1/fCLK
tdCLKH
tdCLKL
1/fs
tLRH
tLRL
tBCK
tBCKH
tBCKL
50%TVDD
dCLK=tdCLKHfs100
or
tdCLKLfs100
50%TVDD
Duty=tLRHfs100
or
tLRLfs100
VIH
VIL
Figure 17. Clock Timing (Slave Mode)
1/fCLK
tCLKH
tCLKL
1/fs
dCLK=tCLKHfCLK100
or
tCLKLfCLK100
50%TVDD
tLRH
Duty=tLRHfs100
50%TVDD
tBCK
tBCKH
tBCKL
dBCK=tBCKH/tBCK100
or
tBCKL/tBCK100
Figure 18. Clock Timing (Master Mode)
50%TVDD
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2016/03