AK5556VN_16 Datasheet, PDF (24/69 Pages) Asahi Kasei Microsystems – 6-Channel Differential 32-bit ADC

[AK5556]
(Ta= 40 - +105 C; AVDD= 4.5-5.5 V, TVDD= 1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”),
VDD18= 1.7-1.98 V (LDOE pin=“L”), C_L= 10 pF)
Parameter
Symbol
Min.
Typ.
Max. Unit
Audio Interface Timing (Master mode) (Figure 23)
DSD Audio Interface Timing
(64fs mode, DSDSEL 1-0 bits = “00”)
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDOL/R (Note 20)
tDCK
-
tDCKL
144
tDCKH
144
tDDD
20
1/64fs
-
-
-
-
ns
-
ns
-
ns
20
ns
DSD Audio Interface Timing
(128fs mode, DSDSEL 1-0 bits = “01”)
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDOL/R (Note 20)
tDCK
-
1/128fs
-
ns
tDCKL
72
-
-
ns
tDCKH
72
-
-
ns
tDDD
10
-
10
ns
DSD Audio Interface Timing
(256fs mode, DSDSEL 1-0 bits = “10”)
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDOL/R (Note 20)
tDCK
-
1/256fs
-
ns
tDCKL
36
-
-
ns
tDCKH
36
-
-
ns
tDDD
10
-
10
ns
Note 18. When the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5556
should be reset by the PDN pin or RSTN bit.
Note 20. tDDD is defined from a falling edge of DCLK “↓” to a DSDOL/R edge when DCKB bit = “0” and it
is defined from a rising edge of DCLK “↑” to a DSDOL/R edge when DCKB bit = “1”.
015099857-E-00
- 24 -
2016/03