AK4626A Datasheet, PDF (26/40 Pages) Asahi Kasei Microsystems – High Performance Multi-channel Audio CODEC

ASAHI KASEI
[AK4626A]
„ Power-Down
The ADC and DACs of AK4626A are placed in the power-down mode by bringing PDN “L” and both digital filters are
reset at the same time. PDN “L” also reset the control registers to their default values. In the power-down mode, the
analog outputs go to VCOM voltage and DZF1-2 pins go to “L”. This reset should always be done after power-up. In case
of the ADC, an analog initialization cycle starts after exiting the power-down mode. Therefore, the output data, SDTO
becomes available after 522 cycles of LRCK clock. In case of the DAC, an analog initialization cycle starts after exiting
the power-down mode. The analog outputs are VCOM voltage during the initialization. Figure 14 shows the sequences of
the power-down and the power-up.
The ADC and all DACs can be powered-down individually by PWADN and PWDAN bits. In this case, the internal
register values are not initialized. When PWADN = “0”, SDTO goes to “L”. When PWDAN = “0”, the analog outputs go
to VCOM voltage and DZF1-2 pins go to “H”. Because some click noise occurs, the analog output should muted
externally if the click noise influences system application.
PDN
ADC Internal
State
DAC Internal
State
ADC In
(Analog)
ADC Out
(Digital)
DAC In
(Digital)
DAC Out
(Analog)
Clock In
MCLK,LRCK,SCLK
Normal Operation
Power-down
Normal Operation
GD ⁽³⁾
Power-down
(4)
“0”data
“0”data
GD(3)
(6)
(7)
Don’t care
DZF1/DZF2
(8)
522/fs ⁽¹⁾
Init Cycle
516/fs (2)
Init Cycle
Normal Operation
Normal Operation
GD
(5)
GD
(6)
10∼11/fs (10)
External
Mute
(9)
Mute ON
Notes:
(1) The analog part of ADC is initialized after exiting the power-down state.
(2) The analog part of DAC is initialized after exiting the power-down state.
(3) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(GD).
(4) ADC output is “0” data at the power-down state.
(5) Click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the click
noise influences system application.
(6) Click noise occurs at the falling edge of PDN and at 512/fs after the rising edge of PDN.
(7) When the external clocks (MCLK, BICK and LRCK) are stopped, the AK4626A should be in the power down
mode.
(8) DZF pins are “L” in the power-down mode (PDN = “L”).
(9) Please mute the analog output externally if the click noise (6) influences system application.
(10) DZF= “L” for 10∼11/fs after PDN= “↑”.
Figure 14. Power-down/up sequence example
MS0397-E-00
- 26 -
2005/06