AK4626A Datasheet, PDF (11/40 Pages) Asahi Kasei Microsystems – High Performance Multi-channel Audio CODEC

ASAHI KASEI
SWITCHING CHARACTERISTICS
(Ta=-40°C∼85°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; C_L=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
256fsn, 128fsd:
fCLK
8.192
Pulse Width Low
tCLKL
27
Pulse Width High
tCLKH
27
384fsn, 192fsd:
fCLK
12.288
Pulse Width Low
tCLKL
20
Pulse Width High
tCLKH
20
512fsn, 256fsd:
fCLK
16.384
Pulse Width Low
tCLKL
15
Pulse Width High
tCLKH
15
LRCK Timing
Normal mode (TDM0= “0”, TDM1= “0”)
Normal Speed Mode
fsn
32
Double Speed Mode
fsd
64
Quad Speed Mode
fsq
120
Duty Cycle
Duty
45
TDM256 mode (TDM0= “1”, TDM1= “0”)
LRCK frequency
fsn
32
“H” time
tLRH
1/256fs
“L” time
tLRL
1/256fs
TDM128 mode (TDM0= “1”, TDM1= “1”)
LRCK frequency
“H” time
“L” time
fsd
tLRH
tLRL
64
1/128fs
1/128fs
Audio Interface Timing
Normal mode (TDM0= “0”, TDM1= “0”)
BICK Period
tBCK
81
BICK Pulse Width Low
tBCKL
32
Pulse Width High
tBCKH
32
LRCK Edge to BICK “↑”
(Note 18)
tLRB
20
BICK “↑” to LRCK Edge
(Note 18)
tBLR
20
LRCK to SDTO(MSB)
BICK “↓” to SDTO
tLRS
tBSD
SDTI1-3,DAUX Hold Time
tSDH
20
SDTI1-3,DAUX Setup Time
tSDS
20
TDM256 mode (TDM0= “1”, TDM1= “0”)
BICK Period
tBCK
81
BICK Pulse Width Low
tBCKL
32
Pulse Width High
tBCKH
32
LRCK Edge to BICK “↑”
(Note 18)
tLRB
20
BICK “↑” to LRCK Edge
(Note 18)
tBLR
20
BICK “↓” to SDTO
tBSD
SDTI1 Hold Time
tSDH
10
SDTI1 Setup Time
tSDS
10
TDM128 mode (TDM0= “1”, TDM1= “1”)
BICK Period
tBCK
81
BICK Pulse Width Low
tBCKL
32
Pulse Width High
tBCKH
32
LRCK Edge to BICK “↑”
(Note 18)
tLRB
20
BICK “↑” to LRCK Edge
(Note 18)
tBLR
20
BICK “↓” to SDTO
tBSD
SDTI1-2 Hold Time
tSDH
10
SDTI1-2 Setup Time
tSDS
10
Notes: 18. BICK rising edge must not occur at the same time as LRCK edge.
[AK4626A]
max
12.288
18.432
24.576
Units
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
48
kHz
96
kHz
192
kHz
55
%
48
kHz
ns
ns
96
kHz
ns
ns
ns
ns
ns
ns
ns
ns
40
ns
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
ns
ns
ns
MS0397-E-00
- 11 -
2005/06