AK4626A Datasheet, PDF (12/40 Pages) Asahi Kasei Microsystems – High Performance Multi-channel Audio CODEC

ASAHI KASEI
[AK4626A]
Parameter
Symbol
min
typ
Control Interface Timing (3-wire Serial mode):
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
CSN “↓” to CCLK “↑”
tCSW
150
tCSS
50
CCLK “↑” to CSN “↑”
Control Interface Timing (I²C Bus mode):
tCSH
50
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
4.7
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
4.0
Clock Low Time
tLOW
4.7
Clock High Time
tHIGH
4.0
Setup Time for Repeated Start Condition
tSU:STA
4.7
SDA Hold Time from SCL Falling
(Note 19)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT 0.25
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
4.0
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
Power-down & Reset Timing
PDN Pulse Width
PDN “↑” to SDTO valid
(Note 20)
(Note 21)
tPD
tPDV
150
522
Notes: 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
20. The AK4626A can be reset by bringing PDN “L” to “H” upon power-up.
21. These cycles are the number of LRCK rising from PDN rising.
22. I²C is a registered trademark of Philips Semiconductors.
max Units
ns
ns
ns
ns
ns
ns
ns
ns
100 kHz
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
1.0
µs
0.3
µs
-
µs
50
ns
ns
1/fs
MS0397-E-00
- 12 -
2005/06