AK1590 Datasheet, PDF (26/36 Pages) Asahi Kasei Microsystems – 1GHz Delta-Sigma Fractional-N Frequency Synthesizer

[AK1590]
< Address 5: GPO >
D[19:2]
0
D1
GPO2
D0
GPO1
Address
0101
GPO2: Set the state of [GPO2] pin
This value controls the General-Purpose Output pin GPO2.
The voltage applied to PVDD pin determines the “High” output level.
D1
Function
Remarks
0 “Low” output from the GPO2 pin
1 “High” output from the GPO2 pin
GPO1: Set the state of [GPO1] pin
This value controls the General-Purpose Output pin GPO1.
The voltage applied to the PVDD pin determines the “High” output level.
D0
Function
Remarks
0
“Low” output from the GPO1 pin
1
“High” output from the GPO1 pin
< Address 6: Offset >
D19 D18
00
D[17:0]
OFST[17:0]
Address
0110
OFST[17:0] : Set the adjustable frequency offset in 2’s complementary representation.
This register designates offset from carrier frequency.
After this register is accessed, {NUM[17:0]} and {INT[14:0]} are recalculated and these recalculated
data are used in delta-sigma and N-divider. When this register is not used, this register must be written
00000 (hexadecimal).
OFFSET register must be written at the lower speed than calculated frequency by
“1/3.5RF Frequency/(INT+7)”. If the writing speed is faster than this, the setting is invalid.
MS1478-E-01
26
2013/2