AK5367A Datasheet, PDF (23/28 Pages) Asahi Kasei Microsystems – 96kHz 24-Bit ΔΣ ADC with 0V Bias Selector

[AK5367A]
SDA
SCL
S
start condition
P
stop condition
Figure 21. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
SCL FROM
MASTER
S
START
CONDITION
not acknowledge
1
2
Figure 22. Acknowledge on the I²C-Bus
acknowledge
8
9
clock pulse for
acknowledgement
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 23. Bit Transfer on the I²C-Bus
MS0967-E-00
- 23 -
2008/05