AK5367A Datasheet, PDF (16/28 Pages) Asahi Kasei Microsystems – 96kHz 24-Bit ΔΣ ADC with 0V Bias Selector

[AK5367A]
■ Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz
(@fs=48kHz) and scales with sampling rate (fs).
■ Power-down
The AK5367A is placed in the power-down mode by bringing the PDN pin = “L” and the digital filter is also reset at the
same time. This reset must always be executed after power-up. At the power-down mode, the VCOM voltage is VSS1.
After exiting the power-down mode, the Charge pump circuit is powered up, then Pre-Amp circuit is automatically
powered up and an analog initialization cycle starts(Figure 10). Therefore, the output data SDTO becomes available after
4388 x LRCK cycles at slave mode, and 4385 x LRCK cycles in master mode. In the initialization, the both channel of
ADC output is “0” of 2’s complement. After the initialization, the ADC output is settled equal to analog input signal.(the
setting time is long as group delay)
Power Supply
(1)
(AVDD, DVDD, CVDD)
PDN
Charge Pump
Internal State
CVEE Pin
Power-down power-up
(5)
0V
-CVDD
ADC
Internal State
Power-down power-up _Initialize
Pre-amp In
(Analog)
(3)
ADC OUT
(Digital)
Clock In
MCLK,LRCK,BICK
“0”data
(1)
Normal Operation
Power-down power-up
(5)
0V
Normal Operation
-CVDD
Normal Operation
(2)
(2)
GD
GD
Power-down ^power-up _Initialize
Normal Operation
(2)
GD
Idle Noise
Idle Noise
(3)
“0”data
(4)
Idle Noise
Notes:
(1) 4388/fs at slave mode, 4385/fs at master mode.
(2) Analog output corresponding to digital input has group delay (GD).
(3) ADC output is “0” data at the power-down mode.
(4) Place the AK5367A in power-down mode if MCLK, BICK and LRCK are not present.
(5) Power-up time of Charge Pump Circuit. 260/fs (slave mode), 257/fs (master mode).
Figure 10. Power-down/up sequence example
MS0967-E-00
- 16 -
2008/05