AK5367A Datasheet, PDF (14/28 Pages) Asahi Kasei Microsystems – 96kHz 24-Bit ΔΣ ADC with 0V Bias Selector

[AK5367A]
OPERATION OVERVIEW
■ System Clock
MCLK, BICK and LRCK clocks are required. The LRCK clock input must be synchronized with MCLK, however the
phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system clock frequency. The
MCLK, BICK and master/slave mode setting are selected by CKS2-0 bits(Table 2).
In slave mode, all external clocks (MCLK, BICK and LRCK) must be present unless the PDN pin = “L”. If these clocks
are not provided, the AK5367A may draw excess current due to its use of internal dynamically refreshed logic. If the
external clocks are not present, place the AK5367A in power-down mode (PDN pin = “L”). In master mode, the master
clock (MCLK) must be provided unless the PDN pin = “L”. It is not necessary to reset by bringing the PDN pin “L” when
clocks and fs are changed. They should be changed after soft mute (SMUTE bit = “1”) to avoid switching noise.
fs
32kHz
44.1kHz
48kHz
96kHz
MCLK
256fs
384fs
512fs
768fs
8.192MHz 12.288MHz 16.384MHz 24.576MHz
11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz
12.288MHz 18.432MHz 24.576MHz 36.864MHz
24.576MHz 36.864MHz
N/A
N/A
Table 1. System Clock Example (N/A: Not available)
Mode CKS2 CKS1 CKS0 Master/Slave
MCLK
0
0
0
0
Slave
256/384fs (32k≤fs≤96k)
512/768fs (32k≤fs≤48k)
1
0
0
1
Reserved
2
0
1
0
Master
256fs (32k≤fs≤96k)
3
0
1
1
Master
512fs (32k≤fs≤48k)
4
1
0
0
Reserved
5
1
0
1
Reserved
6
1
1
0
Master
384fs (32k≤fs≤96k)
7
1
1
1
Master
768fs (32k≤fs≤48k)
Note 18. The SDTO output is 16bit when BICK=32fs input.
Table 2. Operation Mode Select
BICK
≥ 48fs or 32fs
(Note 18)
(default)
64fs
64fs
64fs
64fs
MS0967-E-00
- 14 -
2008/05