AK4951EG Datasheet, PDF (23/30 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

■ Timing Diagram
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
LRCK
tLRCKH
tLRCKL
1/fBCK
50%TVDD
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
BICK
50%TVDD
tBCKH
tBCKL
Duty = tBCKH x fBCK x 100
tBCKL x fBCK x 100
Figure 5. Clock Timing (PLL/EXT Master mode)
[AK4951]
LRCK
50%TVDD
BICK
tBLR
tLRD
tBCKL
tBSD
50%TVDD
SDTO
50%TVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 6. Audio Interface Timing (PLL/EXT Master mode)
014004561-E-00-PB
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2014/08