AK4951EG Datasheet, PDF (20/30 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951]
■ Switching Characteristics
(Ta=25C; fs=48kHz; C_L=20pF; AVDD=2.83.5V, SVDD=1.8~5.5V, DVDD=1.6~1.98V, TVDD=1.6 or
(DVDD-0.2)3.5V)
Parameter
Symbol
min
typ
max Unit
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency PLL3-0 bits = “0100” fCLK
-
11.2896
-
MHz
PLL3-0 bits = “0101” fCLK
-
12.288
-
MHz
PLL3-0 bits = “0110” fCLK
-
12
-
MHz
PLL3-0 bits = “0111” fCLK
-
24
-
MHz
PLL3-0 bits = “1100” fCLK
-
13.5
-
MHz
PLL3-0 bits = “1101” fCLK
-
27
-
MHz
Pulse Width Low
tCLKL 0.4/fCLK
-
-
s
Pulse Width High
tCLKH 0.4/fCLK
-
-
s
LRCK Output Timing
Frequency
fs
-
Table 7
-
Hz
Duty Cycle
Duty
-
50
-
%
BICK Output Timing
Frequency BCKO bit = “0”
fBCK
-
32fs
-
Hz
BCKO bit = “1”
fBCK
-
64fs
-
Hz
Duty Cycle
dBCK
-
50
-
%
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency PLL3-0 bits = “0010”
fs
-
fBCK/32
-
Hz
PLL3-0 bits = “0011”
fs
-
fBCK/64
-
Hz
Duty
Duty
45
-
55
%
BICK Input Timing
Frequency PLL3-0 bits = “0010” fBCK
0.256
-
1.536 MHz
PLL3-0 bits = “0011” fBCK
0.512
-
3.072 MHz
Pulse Width Low
tBCKL 0.4/fBCK
-
-
s
Pulse Width High
tBCKH 0.4/fBCK
-
-
s
External Slave Mode
MCKI Input Timing
Frequency
CM1-0 bits = “00”
fCLK
-
256fs
-
Hz
CM1-0 bits = “01”
fCLK
-
384fs
-
Hz
CM1-0 bits = “10”
fCLK
512fs
Hz
CM1-0 bits = “11”
fCLK
-
1024fs
-
Hz
Pulse Width Low
tCLKL 0.4/fCLK
-
-
s
Pulse Width High
tCLKH 0.4/fCLK
-
-
s
LRCK Input Timing
Frequency
CM1-0 bits = “00”
fs
8
-
48
kHz
CM1-0 bits = “01”
fs
8
-
48
kHz
CM1-0 bits = “10”
fs
8
-
48
kHz
CM1-0 bits = “11”
fs
8
-
24
kHz
Duty
Duty
45
-
55
%
BICK Input Timing
Frequency
fBCK
32fs
-
64fs
Hz
Pulse Width Low
tBCKL
130
-
-
ns
Pulse Width High
tBCKH
130
-
-
ns
014004561-E-00-PB
- 20 -
2014/08