AK4951EG Datasheet, PDF (22/30 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951]
Parameter
Control Interface Timing (I²C Bus)
Symbol min typ max Unit
SCL Clock Frequency
fSCL
-
-
400 kHz
Bus Free Time Between Transmissions
tBUF 1.3
-
-
s
Start Condition Hold Time (prior to first clock pulse)
tHD:STA 0.6
-
-
s
Clock Low Time
tLOW 1.3
-
-
s
Clock High Time
tHIGH 0.6
-
-
s
Setup Time for Repeated Start Condition
tSU:STA 0.6
-
-
s
SDA Hold Time from SCL Falling (Note 30)
tHD:DAT 0
-
-
s
SDA Setup Time from SCL Rising
tSU:DAT 0.1
-
-
s
Rise Time of Both SDA and SCL Lines
tR
-
-
0.3 s
Fall Time of Both SDA and SCL Lines
tF
-
-
0.3 s
Setup Time for Stop Condition
tSU:STO 0.6
-
-
s
Capacitive Load on Bus
Cb
-
-
400 pF
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
-
50 ns
Control Interface Timing (3-wire Serial: AK4951EG)
CCLK Period
tCCK 200
-
-
ns
CCLK Pulse Width Low
Pulse Width High
tCCKL 80
-
tCCKH 80
-
-
ns
-
ns
CDTIO Setup Time
tCDS 40
-
-
ns
CDTIO Hold Time
CSN “H” Time
tCDH 40
-
tCSW 150
-
-
ns
-
ns
CSN Edge to CCLK “” (Note 31)
tCSS
50
-
-
ns
CCLK “” to CSN Edge (Note 31)
tCSH 50
-
-
ns
CCLK “” to CDTIO (at Read Command)
tDCD
-
-
70 ns
CSN “” to CDTIO (Hi-Z) (at Read Command) (Note 32) tCCZ
-
-
70 ns
Power-down & Reset Timing
PDN Accept Pulse Width
(Note 33)
tAPD 200
-
-
ns
PDN Reject Pulse Width
(Note 33)
tRPD
-
-
50 ns
PMADL or PMADR “” to SDTO valid (Note 34)
ADRST1-0 bits =“00”
tPDV
- 1059 - 1/fs
ADRST1-0 bits =“01”
ADRST1-0 bits =“10”
tPDV
tPDV
-
267
- 1/fs
-
531
- 1/fs
ADRST1-0 bits =“11”
tPDV
-
135
- 1/fs
VCOM Voltage
Rising Time
(Note 35)
tRVCM -
0.6
Note 29. I²C Bus is a trademark of NXP B.V.
Note 30. Data must be held for sufficient time to bridge the 300ns transition time of SCL.
2.0 ms
Note 31. CCLK rising edge must not occur at the same time as CSN edge.
Note 32. It is the time of 10% potential change of the CDTIO pin when R_L = 1kΩ (pull-up or TVDD).
Note 33. The AK4951 can be reset by the PDN pin = “L”. The PDN pin must be held “L” for more than 200ns
for a certain reset. The AK4951 is not reset by the “L” pulse less than 50ns.
Note 34. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.
Note 35. All analog blocks including PLL block are powered up after the VCOM voltage (VCOM pin) rises up.
An external capacitor of the VCOM pin is 2.2F and the REGFIL pin is 2.2F. The capacitance
variation should be ±50%.
014004561-E-00-PB
- 22 -
2014/08