AK4358 Datasheet, PDF (22/35 Pages) Asahi Kasei Microsystems – 192 KHZ 24 BIT 8 CH DAC WITH DSD INPUT

ASAHI KASEI
[AK4358]
„ System Reset
The AK4358 should be reset once by bringing PDN= ”L” upon power-up. The analog section exits power-down mode by
MCLK input and then the digital section exits power-down mode after the internal counter counts MCLK during 4/fs.
„ Power-down
The AK4358 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z).
Figure 6 shows an example of the system timing at the power-down and power-up.
Each DAC can be powered down by each power-down bit (PW1-3) “0”. In this case, the internal register values are not
initialized and the analog output is Hi-Z. Because some click noise occurs, the analog output should be muted externally
if the click noise influences system application.
PDN
Internal
State
D/A In
(Digital)
D/A Out
(Analog)
Clock In
MCLK, LRCK, BICK
DZF
Normal Operation
Power-down
“0” data
GD (1)
(3) (2)
(4)
Don’t care
(6)
Normal Operation
GD (1)
(3)
External
MUTE
(5)
Mute ON
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influence system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (PDN = “L”).
Figure 15. Power-down/up Sequence Example
MS0203-E-00
- 22 -
2003/02