AK4358 Datasheet, PDF (15/35 Pages) Asahi Kasei Microsystems – 192 KHZ 24 BIT 8 CH DAC WITH DSD INPUT

ASAHI KASEI
[AK4358]
DCKS
MCLK
DCLK
0
512fs
64fs
1
768fs
64fs
Table 9. System Clock (fs=44.1kHz)
„ Audio Serial Interface Format
1) PCM Mode
When PCM mode, data is shifted in via the SDTI1-4 pins using BICK and LRCK inputs. The DIF0-2 as shown in Table
10 can select five serial data modes. Initial value of DIF0-2 bits is “010” and DIF0 bit is ORed with DIF0 pin. In all
modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of BICK. Mode 2 can be used
for 16/20 MSB justified formats by zeroing the unused LSBs.
When TDM0 = “1”, the audio interface becomes TDM mode. In TDM256 mode (TDM1 = “0”, Table 11), the serial data
of all DAC (eight channels) is input to the SDTI1 pin. The input data to SDTI2-4 pins is ignored. BICK should be fixed to
256fs. “H” time and “L” time of LRCK should be 1/256fs at least. The serial data is MSB-first, 2’s compliment format.
The input data to SDTI1 pin is latched on the rising edge of BICK. In TDM128 mode (TDM1 = “1”, Table 12), the serial
data of DAC (four channels; L1, R1, L2, R2) is input to the SDTI1 pin. Other four data (L3, R3, L4, R4) is input to the
SDTI2. The input data to SDTI3-4 pins is ignored. BICK should be fixed to 128fs.
Mode
0
1
2
3
4
TDM1
0
0
0
0
0
TDM0
0
0
0
0
0
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
SDTI Format
16bit LSB Justified
20bit LSB Justified
24bit MSB Justified
24bit I²S Compatible
24bit LSB Justified
LRCK
H/L
H/L
H/L
L/H
H/L
BICK
≥32fs
≥40fs
≥48fs
≥48fs
≥48fs
Table 10. Audio Data Formats (Normal mode)
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
Default
LRCK
BICK
(32fs)
SDTI
Mode 0
BICK
(64fs)
SDTI
Mode 0
01
10 11 12 13 14 15 0 1
15 14
01
6 5 4 3 2 1 0 15 14
14 15 16 17
31 0 1
Don’t care
15 14
15:MSB, 0:LSB
Lch Data
0 Don’t care
10 11 12 13 14 15 0 1
6 5 4 3 2 1 0 15 14
14 15 16 17
31 0 1
15 14
0
Rch Data
Figure 1. Mode 0 Timing
MS0203-E-00
- 15 -
2003/02