AK4358 Datasheet, PDF (13/35 Pages) Asahi Kasei Microsystems – 192 KHZ 24 BIT 8 CH DAC WITH DSD INPUT

ASAHI KASEI
[AK4358]
„ D/A Conversion Mode
OPERATION OVERVIEW
The AK4358 can perform D/A conversion for both PCM data and DSD data. When DSD mode, DSD data can be input
from DCLK, DSDL1-4 and DSDR1-4 pins. When PCM mode, PCM data can be input from BICK, SDTI1-4 and LRCK
pins. PCM/DSD mode changes by D/P bit. When PCM/DSD mode changes by D/P bit, the AK4358 should be reset by
RSTN bit, PW bit (PW1=PW2=PW3=PW4= “0”) or PDN pin. It takes about 2/fs to 3/fs to change the mode.
„ System Clock
D/P bit
0
1
DAC Output
PCM
DSD
Table 1. DSD/PCM Mode Control
1) PCM Mode
The external clocks, which are required to operate the AK4358, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS =
“0”: Register 00H), the sampling speed is set by DFS0/1(Table 2). The frequency of MCLK at each sampling speed is set
automatically. (Table 3~Table 5). In Auto Setting Mode (ACKS = “1”: Default), as MCLK frequency is detected
automatically (Table 6), and the internal master clock becomes the appropriate frequency (Table 7), it is not necessary to
set DFS0/1. When ACKSN = “H”, regardless of ACKS bit setting the AK4358 operates by Manual Setting Mode. When
ACKSN = “L”, ACKS bit setting is valid.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4358 is in the normal operation
mode (PDN= ”H”). If these clocks are not provided, the AK4358 may draw excess current and may fall into unpredictable
operation. This is because the device utilizes dynamic refreshed logic internally. The AK4358 should be reset by PDN =
“L” after threse clocks are provided. If the external clocks are not present, the AK4358 should be in the power-down
mode (PDN= ”L”). After exiting reset(PDN = “↑”) at power-up etc., the AK4358 is in the power-down mode until MCLK
is input. DSD interface signals (DCLK, DSDL1-4, DSDR1-4) are fixed to “H” or “L”.
DFS1
0
0
1
DFS0
0
1
0
Sampling Rate (fs)
Normal Speed Mode
8kHz~48kHz
Double Speed Mode
60kHz~96kHz
Quad Speed Mode
120kHz~192kHz
Table 2. Sampling Speed (Manual Setting Mode)
Default
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920MHz
11.2896MHz
12.2880MHz
MCLK
384fs
512fs
12.2880MHz 16.3840MHz
16.9344MHz 22.5792MHz
18.4320MHz 24.5760MHz
768fs
24.5760MHz
33.8688MHz
36.8640MHz
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
Table 3. System Clock Example (Normal Speed Mode @Manual Setting Mode)
MS0203-E-00
- 13 -
2003/02