AK4356 Datasheet, PDF (20/29 Pages) Asahi Kasei Microsystems – 192kHz 24 Bit IX-CHANNEL DAC FOR DVD-AUDIO

ASAHI KASEI
[AK4356]
n Serial Control Interface
The AK4356 can control its functions via both pins and registers. CKS2-0, DIF2-0, DFS0, DZFE and SMUTE pins are
ORed with their registers.
Internal registers may be written to the 3 wire uP interface pins: CSN, CCLK & CDTI. The data on this interface consists
of Chip address (2bits, CAD0/1), Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first,
8bits). Address and data is clocked in on the rising edge of CCLK. Data is latched after a low-to-high transition of CSN.
The clock speed of CCLK is 5MHz(max). The CSN pin should be held to “H” except for access.
The chip address is determined by the state of the CAD0 and CAD1 inputs. PDN = “L” initializes the registers to their
default values. Writing “0” to the RSTN bit can initialize the internal timing circuit. But in this case, the register data is not
be initialized.
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (C1=CAD1, C0=CAD0)
R/W: Read/Write (Fixed to “1” : Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 7. Control I/F Timing
Function
Pin set-up
Register set-up
Double Speed
O
O
4 times Speed
X
O
De-emphasis
X
O
DZFE
O
O
DZFM
X
O
SMUTE
O
O
Attenuator
X
O
Slow roll-off response
X
O
Table 6. Function Table (O: Supported, X: Not supported)
Note: Writing to control register is inhibited when PDN = “L” or the MCLK is not fed.
M0072-E-01
- 20 -
1999/09