AK4421A Datasheet, PDF (14/19 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output

[AK4421A]
■ Reset Function
When the MCLK or LRCK stops, the AK4421A is placed in reset mode and its analog outputs are set to VSS (0V, typ).
When the MCLK and LRCK are restarted, the AK4421A returns to normal operation mode.
Internal
State
Normal Operation
Reset
Normal Operation
D/A In
(Digital)
D/A Out
(Analog)
(1)
(3)
VSS
(3)
GD (2)
<Case1:MCLK Stop>
Clock In
MCLK, BICK, LRCK
(4) _{MCLK Stop}
DZF
<Case2:LRCK Stop>
Clock In
MCLK, BICK, LRCK
(5)
(4) _{LRCK Stop}
DZF
<Case3:BICK Stop>
Clock In
MCLK, BICK, LRCK
(5)
(4) BICK Stop
DZF
(5)
Notes:
(1) Digital data can be stopped. The click noise after MCLK, LRCK and BICK are input again can be reduced by
inputting the “0” data during this period.
(2) The analog output corresponding to a specific digital input has group delay (GD).
(3) No audible click noise occurs under normal conditions.
(4) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK, LRCK or BICK is stopped).
(5) The DZF pin is set to “L” in the reset mode.
Figure 9. Reset Timing Example
MS1086-E-01
- 14 -
2009/09