AK4421A Datasheet, PDF (13/19 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output

[AK4421A]
■ System Reset
The AK4421A is in power down mode upon power-up. The MLCK should be input after the power supplies are ramped
up. The AK4421A is in power-down mode until LRCK are input.
Power Supply
(VDD, CVDD)
(6)
MCLK
Low
Analog
Circuit
Power down
20 us
(1)
Digital
Circuit
Charge Pump
Circuit
Power down
(2)
Power down
Charge Pump
Counter circuit
Power-up
2, 3
LRCK
Power-up
Power-up
(3)
Time A
D/A In
(Digital)
“0” data
D/A Out
(Analog)
MUTE (D/A Out)
(4)
(5)
DZF
Notes:
(1) Approximately 20us after a MCLK input is detected, the internal analog circuit is powered-up.
(2) The digital circuit is powered-up after 2 or 3 LRCK cycles following the detection of MCLK.
(3) The charge pump counter starts after the charge pump circuit is powered-up. The DAC outputs a valid analog signal
after Time A.
Time A = 1024/ (fs x 16): Normal speed mode
Time A = 1024/ (fs x 8): Double speed mode
Time A = 1024/ (fs x 4): Quadruple speed mode
(4) No audible click noise occurs under normal conditions.
(5) The DZF pin is “L” in the power-down mode.
(6) The power supply must be powered-up when the MCLK pin is “L”. MCLK must be input after 20us when the power
supply voltage achieves 80% of VDD. If not, click noise may occur at a different time from this figure.
Figure 8. System Reset Diagram
MS1086-E-01
- 13 -
2009/09