AK4254 Datasheet, PDF (14/22 Pages) Asahi Kasei Microsystems – Capacitor-less Video Amp with 7:2 Video Switch

ASAHI KASEI
[AK4254]
2. I²C Bus mode
The AK4254 supports the fast-mode I2C-bus (max: 400kHz).
2-1. WRITE operations
Figure 6 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates the START condition (Figure 12). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant six bits of the slave address are fixed as “00100”. The next bits are CAD0-1 (device address
bit). This bit identifies the specific device on the bus. The hard-wired input pin (CAD0-1 pins) sets these device address
bits(Figure 7). If the slave address matches that of the AK4254, the AK4254 generates an acknowledge and the operation
is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the
acknowledge clock pulse (Figure 13). A R/W bit value of “1” indicates that the read operation is to be executed. A “0”
indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4254. The format is MSB first, and those most
significant 7-bits are fixed to zeros (Figure 8). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 9). The AK4254 generates an acknowledge after each byte has been received. A data transfer is always
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is
HIGH defines a STOP condition (Figure 12).
The AK4254 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4254
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 1-bit address counter is
incremented by one, and the next data is automatically taken into the next address.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 14) except for the START and STOP
conditions.
S
T
S
A
R/W= "0"
T
R
O
T
P
SDA
Slave
S _Address
Sub
Address(n)
Data(n)
Data(n+1)
Data(n+x)
P
A
A
A
A
A
A
C
C
C
C
C
C
K
K
K
K
K
K
Figure 6. Data Transfer Sequence at the I²C-Bus Mode
0
0
1
0
0 CAD1 CAD0 R/W
Figure 7. The First Byte (Those CAD1/0 should match with CAD1/0 pins)
0
0
0
0
0
0
0
A0
Figure 8. The Second Byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 9. Byte Structure after the Second Byte
MS0586-E-01
- 14 -
2007/08