AK4341 Datasheet, PDF (13/18 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output

ASAHI KASEI
[AK4341]
■ Reset Function
When the MCLK or LRCK stops during the normal operation (PDN pin =”H”), the AK4341 is placed in the reset mode
and its analog outputs are set to VCOM voltage (VDD). When the MCLK and LRCK are restarted, the AK4341 return to
the normal operation mode. The BICK can be stopped when MCLK or LRCK is stopped but shouldn’t be stopped when
MCLK and LRCK are supplied.
PDN pin
(1)
Internal
State
Power-down
Normal Operation
D/A In
(Digital)
Power-down
D/A Out
(Analog)
Hi-Z
(4)
<Case1:MCLK Stop>
Clock In
MCLK, BICK, LRCK
GD (2)
Reset
(3)
(4)
VCOM
Normal Operation
GD (2)
(4)
(5) _{MCLK Stop}
External
MUTE
(6)
(6)
(6)
<Case2:LRCK Stop>
Clock In
MCLK, BICK, LRCK
(5) (7) _{LRCK Stop}
External
MUTE
(6)
(6)
(6)
Notes:
(1) PDN pin should be “L” for 150ns or more after power-on.
(2) The analog output corresponding to digital input has the group delay (GD).
(3) Digital data can be stopped. The click noise after the MCLK and LRCK are input again can be reduced by
inputting the “0” data during this period.
(4) Click noise occurs within 20usec and 20usec +(3∼4LRCK) after the edges(“↑ ↓”) of the PDN pin and MCLK
starting. The noises also occur when MCLK or LRCK is stopped and within 20usec after stopping.
(5) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK or LRCK is stopped).
(6) Mute externally if the click noises (4) cause problem.
(7) The AK4341 detects the stop of LRCK by the ratio MCLK/LRCK > 2048. If the LRCK is input, when LRCK is
stopping, then the AK4341 exits the reset mode.
Figure 5. Reset Timing Example
MS0558-E-01
- 13 -
2007/03