AK4440 Datasheet, PDF (11/31 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit 8ch DAC with 2Vrms Output

[AK4440]
OPERATION OVERVIEW
■ System Clock
The external clocks, which are required to operate the AK4440, are MCLK, LRCK and BICK. The master clock
(MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital
interpolation filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting
Mode (ACKS bit = “0”: Register 00H), the sampling speed is set by DFS1-0 bits (Table 1). The frequency of MCLK
for each sampling speed is set automatically. (Table 2~Table 4) In auto setting mode (ACKS bit = “1”: Default), as
MCLK frequency is detected automatically (Table 5), and the internal master clock becomes the appropriate frequency
(Table 6), it is not necessary to set DFS1-0 bits.
In parallel control mode, the sampling speed can be set by only the ACKS pin. When ACKS pin = “L”, the AK4440
operates by Normal Speed Mode. When ACKS pin = “H”, auto setting mode is enabled. The parallel control mode does
not support 128fs and 192fs of double speed mode.
The AK4440 is automatically placed in power saving mode when MCLK, LRCK and BICK stop during normal
operation mode, and the analog output is forced to 0V(typ). When MCLK, LRCK and BICK are input again, the
AK4440 is powered up. After power-up, the AK4440 is in the power-down mode until MCLK, LRCK and BICK are
input.
DFS1 bit
0
0
1
DFS0 bit
0
1
0
Sampling Rate (fs)
Normal Speed Mode
8kHz~48kHz
Double Speed Mode
60kHz~96kHz
Quad Speed Mode
120kHz~192kHz
Table 1. Sampling Speed (Manual Setting Mode)
(default)
LRCK
MCLK
BICK
fs
256fs
384fs
512fs
768fs
1152fs
64fs
32.0kHz 8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 36.8640MHz 2.0480MHz
44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz
N/A
2.8224MHz
48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz
N/A
3.0720MHz
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode) (N/A: Not available)
MS1088-E-01
- 11 -
2011/03