TSI-2 Datasheet, PDF (59/61 Pages) Agere Systems – 2k x 2k Time-Slot Interchanger

Data Sheet, Revision 3
September 21, 2005
TSI-2
2k x 2k Time-Slot Interchanger
Table 8-2. High_Control_Word (Read/Write)
Address
Bit
Name/Description
Default
0x10002—0x17FFE 15:11 Reserved.
0x0
10 Test_Pattern_Monitor_Enable.
—
0 = The TPM is disable for this time slot.
1 = This bit causes data for this time slot to be sent to the test pattern monitor for
checking.
9:8 Time_Slot_Mode. This field defines in which of the following modes the time slot —
will operate:
00 = Low latency.
01 = Frame integrity.
10 = Alternate data.
11 = TPG data.
7 Reserved.
—
Note: This bit must be set to zero.
6:5 Unused.
—
4 General_Purpose_Bit. This is a general-purpose read/write bit. It causes no
—
action within the device.
3:0 Unused.
—
Agere Systems Inc.
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