TSI-2 Datasheet, PDF (1/61 Pages) Agere Systems – 2k x 2k Time-Slot Interchanger

Data Sheet, Revision 3
September 21, 2005
TSI-2
2k x 2k Time-Slot Interchanger
1 Introduction
The last issue of this data sheet was August 31, 2005. A change history is included in Section 11 Change History on page
61. Red change bars have been installed on all text, figures, and tables that were added or changed. All changes to the text
are highlighted in red. Changes within figures, and the figure title itself, are highlighted in red, if feasible. Formatting or
grammatical changes have not been highlighted. Deleted sections, paragraphs, figures, or tables will be specifically
mentioned.
This document consists of two major sections:
„ The TSI-2 device hardware description. This section contains ball information, operating conditions, dc electrical charac-
teristics, timing diagrams, ac characteristics, and packaging information.
„ The TSI-2 device register description. This section contains register information.
1.1 Related Documents
The documentation package for this device consists of the following documents:
„ The TSI-2 2k x 2k Time-Slot Interchanger Product Brief, the TSI Family Selection Guide, the TSI-2 2k x 2k Time-Slot
Interchanger Data Sheet (this document), and the TSI-2 Time-Slot Interchanger System Design Guide.
These documents are available on the public website shown below.
If the reader displays this document using Acrobat Reader ^®, clicking on any blue text will bring the reader to that reference
point.
To access related documents, including the documents mentioned above, please go to the following public website, or con-
tact your Agere representative (see the last page of this document).
http://www.agere.com/telecom/time_slot_interchangers.html
1.2 Block Diagram and High-Level Interface Definition
TEST ACCESS
PORT
32
RECEIVE
CHI
TEST PATTERN
MONITOR
2k x 2k Switch Fabric
DATA
STORE
TEST PATTERN
GENERATOR
32
TRANSMIT
CHI
CLOCK
GENERATOR
WRITE ADDRESS
COUNTER
CONNECTION
STORE
READ ADDRESS
COUNTER
MICROPROCESSOR
INTERFACE
Figure 1-1. Block Diagram and High-Level Interface Definition