FW322061394 Datasheet, PDF (37/92 Pages) Agere Systems – PCI PHY/Link Open Host Controller Interface

Data Sheet, Rev. 1
December 2005
FW322 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
OHCI Registers
The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory mapped into a
2 Kbyte region of memory pointed to by the OHCI Base Address register located at offset 10h in PCI configuration
space. These registers are the primary interface for controlling the FW322 1394 OHCI function. This section pro-
vides a summary of the registers within this interface and a description of the individual bit fields within each regis-
ter. For more details regarding these registers and bits, please refer to the 1394 Open Host Controller Interface
Specification, Rev. 1.1.
In addition to regular read/write registers, there are several pairs of set and clear registers implemented within the
OHCI register interface. For each pair of set and clear registers, there are two addresses that correspond to indi-
vidual set/clear registers: RegisterSet and RegisterClear. Refer to Table 20 for a listing of these registers. A 1 bit
written to RegisterSet causes the corresponding bit in the register to be set, while a 0 bit leaves the corresponding
bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the register to be reset, while a 0 bit
leaves the corresponding bit unaffected. Typically, a read from either RegisterSet or RegisterClear returns the con-
tents of the set or clear register. However, in some instances, reading the RegisterClear provides a masked version
of the set or clear register. The Interrupt Event register is an example of this behavior.
The following FW322 OHCI register definitions are based on version 1.1 of the 1394 Open Host Controller
Specification.
Table 19. OHCI Register Map
DMA
Context
Register Name
—
OHCI Version
Global Unique ID ROM
Asynchronous Transmit Retries
CSR Data
CSR Compare Data
CSR Control
Configuration ROM Header
Bus Identification
Bus Options
Global Unique ID High
Global Unique ID Low
Reserved
Reserved
Configuration ROM Map
Posted Write Address Low
Posted Write Address High
Vendor Identification
Reserved
Host Controller Control
Reserved
Reserved
Reserved
Abbreviation
Version
GUID_ROM
ATRetries
CSRData
CSRCompareData
CSRControl
ConfigROMhdr
BusID
BusOptions
GUIDHi
GUIDLo
—
—
ConfigROMmap
PostedWriteAddressLo
PostedWriteAddressHi
VendorID
—
HCControlSet
HCControlClear
—
—
—
Offset
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
Reserved
50h
54h
58h
5Ch
60h
OHCI
Specification
Reference
5.2
5.3
5.4
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
—
—
5.5.6
13.2.8.1
5.6
—
5.7
—
—
—
Agere Systems Inc.
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