FW322061394 Datasheet, PDF (33/92 Pages) Agere Systems – PCI PHY/Link Open Host Controller Interface

Data Sheet, Rev. 1
December 2005
FW322 06 1394a
PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
PCI OHCI Control Register
The PCI OHCI Control register is defined in Section A.3.7 of the 1394 Open Host Controller Interface
Specification and provides a bit for big endian PCI support. Note that the GLOBAL_SWAP bit is loaded from the
serial EEPROM on powerup.
Offset:
Default:
Type:
Reference:
40h
0000 0000h
Read/write
1394 Open Host Controller Interface Specification, Rev. 1.1, Section A.3.7
Table 14. PCI OHCI Control Register Description
Bit
Field Name
Type
Description
31:1
Reserved
R Reserved. Bits 31:1 return 0s when read.
0
GLOBAL_SWAP RW When this bit is set, all quadlets read from the FW322 as well as any
data written to the PCI bus by the FW322 is byte swapped. This
excludes PCI Config registers and CardBus Function Event registers
(they are not swapped under any circumstances). However, OHCI
registers are byte swapped when this bit is set.
Capability ID and Next Item Pointer Register
The Capability ID and Next Item Pointer register identifies the linked list capability item and provides a pointer to
the next capability item.
Offset:
Default:
Type:
Reference:
44h
0001h
Read only
PCI Local Bus Specification, Rev. 2.2, Sections 6.8.1.1, 6.8.1.2 and 1394 Open Host Controller
Interface Specification, Rev. 1.1, Sections A.3.8.1 and A.3.8.2
Table 15. Capability ID and Next Item Pointer Register Description
Bit
Field Name
Type
Description
15:8
NEXT_ITEM
R Next Item Pointer. The FW322 supports only one additional capability
that is communicated to the system through the extended capabilities
list; thus, this field returns 00h when read.
7:0
CAPABILITY_ID
R Capability Identification. This field returns 01h when read, which is
the unique ID assigned by the PCI SIG for PCI power management
capability.
Agere Systems Inc.
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