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FW322061394 Datasheet, PDF (1/92 Pages) Agere Systems – PCI PHY/Link Open Host Controller Interface | |||
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FW322 06 1394a
PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
December 2005
â¢
Features
 1394a-2000 OHCI link and PHY core function in a
single device:
â Single-chip link and PHY enable smaller, simpler,
more efficient motherboard and add-in card
designs
â Enables lower system costs
â Leverages proven 1394a-2000 PHY core design
â Demonstrated compatibility with current
Microsoft® Windows® drivers and common appli-
cations
â Demonstrated interoperability with existing, as
well as older, 1394 consumer electronics and
peripherals products
â Feature-rich implementation for high perfor-
mance in common applications
â Supports low-power system designs (CMOS
implementation, power management features)
â Provides LPS, LKON, and CNA outputs to sup-
port legacy power management implementations
 OHCI:
â Complies with the 1394 OHCI 1.1 Specification
â OHCI 1.0 backwards compatibleâconfigurable
via EEPROM to operate in either OHCI 1.0 or
OHCI 1.1 mode
â Complies with Microsoft Windows logo program
system and device requirements
â Listed on Windows hardware compatibility list
http://www.microsoft.com/windows/catalog/
â Compatible with Microsoft Windows and
MacOS ® operating systems
â 4 Kbyte isochronous transmit FIFO
â 2 Kbyte asynchronous transmit FIFO
â 4 Kbyte isochronous receive FIFO
â 2 Kbyte asynchronous receive FIFO
â Dedicated asynchronous and isochronous
descriptor-based DMA engines
â Eight isochronous transmit contexts
â Eight isochronous receive contexts
â Prefetches isochronous transmit data
â Supports posted write transactions
â Supports parallel processing of incoming phys-
ical read and write requests
â Supports notification (via interrupt) of a failed
register access
â May be used without an EEPROM when the sys-
tem BIOS is programmed with the EEPROM con-
tents.
 1394a-2000 PHY core:
â Compliant with IEEE ® 1394a-2000, Standard for
a High Performance Serial Bus (Supplement)
â Provides two fully compliant cable ports, each
supporting 400 Mbits/s, 200 Mbits/s, and
100 Mbits/s traffic
â Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders
â While unpowered and connected to the bus, will
not drive TPBIAS on a connected port even if
receiving incoming bias voltage on that port
â Does not require external filter capacitor for PLL
â Supports link-on as a part of the internal
PHY core-link interface
â 25 MHz crystal oscillator and internal PLL
provide a 50 MHz internal link-layer controller
clock as well as transmit/receive data at
100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.
â Interoperable across 1394 cable with 1394 phys-
ical layers (PHY core) using 5 V supplies
â Provides node power-class information signaling
for system power management
â Supports ack-accelerated arbitration and fly-by
concatenation
â Supports arbitrated short bus reset to improve
utilization of the bus
â Fully supports suspend/resume
â Supports connection debounce
â Supports multispeed packet concatenation
â Supports PHY pinging and remote PHY access
packets
â Reports cable power fail interrupt when voltage
at CPS pin falls below 7.5 V
â Provides separate cable bias and driver termina-
tion voltage supply for each port
 Link:
â Cycle master and isochronous resource
manager capable
â Supports 1394a-2000 acceleration features
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