W3020 Datasheet, PDF (32/44 Pages) Agere Systems – GSM Multiband RF Transceiver

W3020 GSM Multiband RF Transceiver
Advance Data Sheet
December 1999
Programming Information (continued)
Filter Tune and dc Offset Correction Timing (continued)
dc Offset Calibration
The dc offset calibration operation is controlled by several bits in the CONFIG and TR registers:
n DS: dc correction skip, in the TR register
n DP: dc precharge only, in the TR register
n C5: dc correction disable, in the CONFIG register
n C7: dc coarse/fine correction, in the CONFIG register
n DT: dc correction time, in the CONFIG register
When the dc correction disable bit (C5) in the CONFIG register is written high, the dc offset correction circuitry
charges to a default value, corresponding to 0 dc offset, and any request for dc offset calibration is ignored. If dc
correction disable = 0, the dc offset calibration is initiated by writing the MO bits in the TR (or MAIN) register to a
value of 111 while dc correction skip (DS) and dc precharge only (DP) are both low. As in the case of the filter
tune, start of dc offset calibration is held off for about 15 µs while the bias circuits and input clock buffer start-up.
If the FTR bit was also written high coincident with entering RX mode, a filter tune is performed first, after which
dc offset calibration begins automatically.
The dc offset calibration runs for a time determined by the dc offset correction time bits DT[0:2] in the CONFIG
register. There are three of these bits, giving the user a choice of eight different correction times.
Upon completion of the dc offset calibration, the 3.25 MHz baseband clock stops and full receive mode is
entered automatically, with the LO1 buffer and LNA (if G0 = 1) being enabled automatically.
If RX mode is entered with dc precharge only (DP = 1) set high, dc offset circuitry runs through a much shorter
calibration routine, after which normal receive mode is entered automatically. The precharge-only operation
functions much the same as the normal calibration operation in that the LO1 buffer and LNA is disabled until
completion of the precharge operation. The 15 µs bias start-up time is still incurred.
The receive circuitry conditions during dc calibration are also controlled by two other bits in the CONFIG register:
n C2: LNA on during dc calibration, when high
n C3: receive LO1 buffer on during dc, calibration when high
For both the standard dc offset calibration cycle and the dc precharge-only operation, it is possible to perform dc
offset calibration with the LNA and/or LO1 buffer on by setting the C2 and C3 bits in the CONFIG register.
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