W3020 Datasheet, PDF (23/44 Pages) Agere Systems – GSM Multiband RF Transceiver

Advance Data Sheet
December 1999
W3020 GSM Multiband RF Transceiver
Programming Information (continued)
TR Register (continued)
Table 15. MO[3:1]: Mode Control
MO3
Bit 22
0
0
0
0
1
1
1
1
MO2
Bit 21
0
0
1
1
0
0
1
1
MO1
Bit 20
0
1
0
1
0
1
0
1
Function
Sleep: All Modules Powerdown
Reserved
Reserved
Reserved
TX PLL Settling Mode (LO1, LO2, TX LO1, and TX LO2 buffers on)
RX PLL Settling Mode (LO1, LO2, RX LO1, and RX LO2 buffers on)
TX ON (TX modulator and mixer, LO1, LO2, TX LO1, and TX LO2 buffers on)
RX ON (RX mixer; LNA, if enabled; IF amplifier; LO1; LO2; RX LO1; and RX LO2
buffers on)*
*If MO bits are set to 111 with the dc correction skip bit low, a dc offset calibration cycle is performed automatically.
Table 16. T6: LO2 Disable
If this bit is set high, the 540 MHz LO2 input buffer
and LO2 PLL will be turned off. This bit will also
disable the 13 MHz clock buffer going to the
baseband amplifier correction circuits. This bit is
provided for testing purposes.
T6
Bit 19
0
1
Function
LO2 Circuit Enabled
LO2 Circuit Disabled
Table 17. T5: LO1 Disable
The T5 bit disables the LO1 circuitry including the
UHF LO1 buffer and bias circuit. This bit is provided
for testing purposes.
T5
Bit 18
0
1
Function
LO1 Circuitry Enabled
LO1 Circuitry Disabled
Table 18. T4: Receive IF Duty Cycle Corrector
Disable
When high, disables duty cycle correction circuit in
the LO2 divide-by-2 circuit for the receive IF
demodulator. This is provided for testing purposes.
T4
Bit 17
0
1
Function
Divide-by-2 Duty Cycle Corrector Enabled
Divide-by-2 Duty Cycle Corrector Disabled
Table 19. T3: Divide-by-3 Duty Cycle Corrector
Disable
When high, disables duty cycle correction circuit in
the GSM1800/1900 transmit IF LO divide-by-3
circuit. This is provided for testing purposes.
T3
Bit 16
0
1
Function
Divide-by-3 Duty Cycle Corrector Enabled
Divide-by-3 Duty Cycle Corrector Disabled
Lucent Technologies Inc.
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