TSI-8 Datasheet, PDF (23/25 Pages) Agere Systems – 8K x 8K Time-Slot Interchanger

Hardware Design Guide, Revision 1
November 2, 2005
TSI-8
8K x 8K Time-Slot Interchanger
MPUCLK
ADDR[15:00]
CS
AS
R/W
DATA[15:00]
PAR[1:0]
DT
t37
t38
t39
t41
t42
t43
t45
t47
t40
t44
t46
t48
t48
t49
Figure 6-17. Microprocessor Port Timing—Write Cycle
Table 6-7. Microprocessor Port Timing—Write Cycle
Parameter
Description
t37
Address Setup
t38
Address Hold
t39
Chip Select Setup
t40
Chip Select Hold
t41
Address Strobe Setup
t42
Address Strobe Hold
t43
R/W Setup
t44
R/W Hold
t45
Data Setup
t46
Data Hold
t47
DT High-Impedance to Valid
t48
DT Clock to Out
t49
DT Valid to High-Impedance
Min
Max
Unit
5
—
ns
1
—
ns
5
—
ns
1
—
ns
5
—
ns
1
—
ns
5
—
ns
1
—
ns
5
—
ns
1
—
ns
1
15
ns
1
7
ns
1
8
ns
Note: Posted writes follow the same timing shown in Figure 6-17 and Table 6-7. A posted write may return a DT prior to the
device completing the write cycle. This allows the microprocessor to continue operation while the TSI-8 completes the
write.
Agere Systems Inc.
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