TSI-8 Datasheet, PDF (18/25 Pages) Agere Systems – 8K x 8K Time-Slot Interchanger

TSI-8
8K x 8K Time-Slot Interchanger
Hardware Design Guide, Revision 1
November 2, 2005
FSYNC
CHICLK
w/ 0 offset
TS0 B0
data sampled
TS0 B1
TS0 B2
w/ ¼ bit offset TS63 B7
TS0 B0
data sampled
TS0 B1
TS0 B2
w/ ½ bit offset
TS63 B7
TS0 B0
data sampled
TS0 B1
TS0 B2
w/ ¾ bit offset
TS63 B7
TS0 B0
data sampled
TS0 B1
w/ bit offset = 1
TS63 B7
data sampled
TS0 B0
TS0 B1
w/ 2¾ bit offset
TS63 B5
TS63 B6
data sampled
TS63 B7
w/ bit offset = 7
TS63 B1
data sampled
TS63 B2
TS63 B3
w/ TS offset = 1,
bit offset = 0
TS63 B0
data sampled
TS63 B1
TS63 B2
w/ TS offset = 13, TS50 B4
bit offset = 3¼
TS50 B5
data sampled
TS50 B6
TS50 B7
w/ TS offset = 63,
bit offset = 7¾
TS0 B0
TS0 B1
data sampled
TS0 B2
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.
Figure 6-9. Typical Receive CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK
FSYNC
CHICLK
w/ 0 offset
TS63 B7
TS0 B0
TS0 B1
w/ ¼ bit offset
TS63 B7
TS0 B0
TS0 B1
w/ ½ bit offset TS63 B6
TS63 B7
TS0 B0
TS0 B1
w/ bit offset = 1
TS63 B6
TS63 B7
TS0 B0
w/ TS offset = 1,
bit offset = 0
TS62 B7
TS63 B0
TS63 B1
w/ TS offset = 63,
bit offset = 7¾
TS63 B7
TS0 B0
TS0 B1
TS0 B2
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.
Figure 6-10. Transmit CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK
18
Agere Systems Inc.