DSP1627 Datasheet, PDF (18/154 Pages) Agere Systems – DSP1627 Digital Signal Processor

DSP1627 Digital Signal Processor
Data Sheet
March 2000
4 Hardware Architecture (continued)
Data Memory Mapping
Table 6. Data Memory Map (Not to Scale)
Decimal
Address
0
Address in
r0, r1, r2, r3
0x0000
Segment
DPRAM[1:6]
6K
0x1800
Reserved
(10K)
16K
16,640
32K
0x4000
0x4100
0x8000
IO
ERAMLO
ERAMHI
64K – 1
0xFFFF
On the data memory side (see Table 6), the six 1K
banks of dual-port RAM are located starting at address
0. Addresses from 0x4000 to 0x40FF reference a 256-
word memory-mapped I/O segment (IO). Addresses
from 0x4100 to 0x7FFF reference the low external data
RAM segment (ERAMLO). Addresses above 0x8000
reference high external data RAM (ERAMHI).
Wait-States
The number of wait-states (from 0 to 15) used when ac-
cessing each of the four external memory segments
(ERAMLO, IO, ERAMHI, and EROM) is programmable
in the mwait register (see Table 36). When the program
references memory in one of the four external seg-
ments, the internal multiplexer is automatically switched
to the appropriate set of internal buses, and the associ-
ated external enable of ERAMLO, IO, ERAMHI, or
EROM is issued. The external memory cycle is auto-
matically stretched by the number of wait-states config-
ured in the appropriate field of the mwait register.
4.5 External Memory Interface (EMI)
The external memory interface supports read/write op-
erations from instruction/coefficient memory, data
memory, and memory-mapped I/O devices. The
DSP1627 provides a 16-bit external address bus,
AB[15:0], and a 16-bit external data bus, DB[15:0].
These buses are multiplexed between the internal bus-
es for the instruction/coefficient memory and the data
memory. Four external memory segment enables,
ERAMLO, IO, ERAMHI, and EROM, select the external
memory segment to be addressed.
If a data memory location with an address between
0x4100 and 0x7FFF is addressed, ERAMLO is asserted
low.
If one of the 256 external data memory locations, with
an address greater than or equal to 0x4000, and less
than or equal to 0x40FF, is addressed, IO is asserted
low. IO is intended for memory-mapped I/O.
If a data memory location with an address greater than
or equal to 0x8000 is addressed, ERAMHI is asserted
low. When the external instruction/coefficient memory is
addressed, EROM is asserted low.
The flexibility provided by the programmable options of
the external memory interface (see Table 36, mwait
Register and Table 38, ioc Register) allows the
DSP1627 to interface gluelessly with a variety of com-
mercial memory chips.
Each of the four external memory segments, ERAMLO,
IO, ERAMHI, and EROM, has a number of wait-states
that is programmable (from 0 to 15) by writing to the
mwait register. When the program references memory
in one of the four external segments, the internal multi-
plexer is automatically switched to the appropriate set of
internal buses, and the associated external enable of
ERAMLO, IO, ERAMHI, or EROM is issued. The exter-
nal memory cycle is automatically stretched by the num-
ber of wait-states in the appropriate field of the mwait
register.
When writing to external memory, the RWN pin goes
low for the external cycle. The external data bus,
DB[15:0], is driven by the DSP1627 starting halfway
through the cycle. The data driven on the external data
bus is automatically held after the cycle unless an exter-
nal read cycle immediately follows.
The DSP1627 has one external address bus and one
external data bus for both memory spaces. Since some
instructions provide the capability of simultaneous ac-
cess to both X space and Y space, some provision must
be made to avoid collisions for external accesses. The
DSP1627 has a sequencer that does the external X ac-
cess first, and then the external Y access, transparently
to the programmer. Wait-states are maintained as
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