DSP1627 Datasheet, PDF (117/154 Pages) Agere Systems – DSP1627 Digital Signal Processor

Data Sheet
March 2000
DSP1627 Digital Signal Processor
11 Timing Characteristics for 3.0 V Operation (continued)
VIH–
OCK _VIL–
VIH–
OLD _VIL–
VOH–
DO* _VOL–
VOH–
SADD _VOL–
VIH–
DOEN _VIL–
VOH–
OBE _VOL–
t80
t82
t81
t85
t83
t84
t85
t88
t87
B0
t94
t92
AD0
t90
t90
B1 B7
BN – 1
t93
AD1
t93
AD7
AS7
t96
t89
t95
5-4796 (F)
* See sioc register, MSB field, to determine if B0 is the MSB or LSB. See sioc register, ILEN field, to determine if the DO word length is 8 bits
or 16 bits.
Figure 55. SIO Passive Mode Output Timing Diagram
Table 140. Timing Requirements for Serial Inputs
Abbreviated Reference
t80
t81
t82
t83
t84
t85
Parameter
Clock Period (high to high)^‡
Clock Low Time (low to high)
Clock High Time (high to low)
Load High Setup (high to high)
Load Low Setup (low to high)
Load Hold (high to invalid)
† Device is fully static; t80 is tested at 200 ns.
‡ For multiprocessor mode, see note in Section 12.10.
Table 141. Timing Characteristics for Serial Outputs
Abbreviated Reference
t87
t88
t89
t90
t92
t93
t94
t95
t96
Parameter
Data Delay (high to valid)
Enable Data Delay (low to active)
Disable Data Delay (high to 3-state)
Data Hold (high to invalid)
Address Delay (high to valid)
Address Hold (high to invalid)
Enable Delay (low to active)
Disable Delay (high to 3-state)
OBE Delay (high to high)
Min
Max
Unit
40
—^†
ns
18
—
ns
18
—
ns
8
—
ns
8
—
ns
0
—
ns
Min
Max
Unit
—
35
ns
—
35
ns
—
35
ns
5
—
ns
—
35
ns
5
—
ns
—
35
ns
—
35
ns
—
35
ns
Lucent Technologies Inc.
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