DSP1627 Datasheet, PDF (100/154 Pages) Agere Systems – DSP1627 Digital Signal Processor

DSP1627 Digital Signal Processor
Data Sheet
March 2000
11 Timing Characteristics for 3.0 V Operation (continued)
11.2 Reset Circuit
The DSP1627 has a powerup reset circuit that automatically clears the JTAG controller upon powerup. If the supply
voltage falls below VDD MIN* and a reset is required, the JTAG controller must be reset—even if the JTAG port isn’t
being used—by applying six low-to-high clock edges on TCK with TMS held high, followed by the usual RSTB and
CKI reset sequence. Figure 60 shows two separate events: an initial powerup and a powerup following a drop in the
power supply voltage.
* See Table 60, Recommended Operating Condiitons.
VDD
RAMP
VDD MIN
0.4 V
t9
t146
t8
VDD MIN
0.4 V
t9
t151
t152
t8
CKI
TCK
TMS ^VIH
t153
t153
RSTB ^VIH
VIL
PINS ^VOH
VOL
t10
t11
t10
t11
5-2253 (F).a
Notes:
See Table 62 for CKI electrical requirements and Table 151 for TCK timing requirements.
When both INT0 and RSTB are asserted, all output and bidirectional pins (except TDO, which 3-states by JTAG control) are put in a 3-state
condition. With RSTB asserted and INT0 not asserted, EROM, ERAMHI, ERAMLO, IO, DSEL, and RWN outputs remain high, and CKO remains
a free-running clock.
TMS and TDI signals have internal pull-up devices.
Figure 36. Powerup Reset and Chip Reset Timing Diagram
Table 108. Timing Requirements for Powerup Reset and Chip Reset
Abbreviated Reference
Parameter
t8
Reset Pulse (low to high)
t9
VDD Ramp
t146
VDD MIN to RSTB Low CMOS
Crystal*
Small-Signal
t151
TMS High
t152
JTAG Reset to
CMOS
RSTB Low
Crystal*
Small-Signal
t153
RSTB (low to high)
Min
6T
—
2T
20
20
6 * TTCK^†
2T
20 ms – 6 * TTCK if 6 * TTCK < 20 ms
0 if 6 * TTCK ≥ 20 ms
20 µs – 6 * TTCK if 6 * TTCK < 20 µs
0 if 6 * TTCK ≥ 20 µs
—
Max
—
10
—
—
—
—
—
—
—
—
—
54
Unit
ns
ms
ns
ms
µs
ns
ns
ns
* With external components as specified in Table 62.
† TTCK = t12 = TCK period. See Table 151 for TCK timing requirements.
100
Lucent Technologies Inc.