OR3LP26B Datasheet, PDF (176/184 Pages) Agere Systems – Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface

ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
Function
VDD2
VDD2
VDD2
VDD2
VSS
VSS
VSS
VSS
VDD2
VDD2
VDD2
VSS
VSS
VSS
VDD2
VDD2
VDD2
VDD2
VSS
VSS
VSS
VSS
VSS
VSS
VDD2
VDD2
VDD2
VDD2
VSS
VSS
VSS
VSS
VSS
VSS
VDD2
VDD2
VDD2
VDD2
PBGA 352
—
—
—
—
—
—
—
—
—
—
—
P11
P12
P13
—
—
—
—
P14
P15
P16
R11
R12
R13
—
—
—
—
R14
R15
R16
T11
T12
T13
—
—
—
—
PBGAM 680
V22
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB13
AB14
AB15
AB16
AB17
AB18
AB19
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the posi-
tion of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
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