OR3LP26B Datasheet, PDF (103/184 Pages) Agere Systems – Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface

Data Sheet
March 2000
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description
Quad Port (continued)
Initiating Target Aborts
There may be a need in an application to initiate a tar-
get abort condition on the PCI bus. In general, this is
asserted for only the most severe cases. The interface
signal, fpga_tabort, is used for this purpose. From the
PCI core's point of view, it needs to know whether to
perform a target abort at the very beginning of a trans-
action, so it is not possible to have a transaction
started, and then assert the fpga_tabort signal. The
signal fpga_tabort needs to be asserted before the
transaction begins, and it was not designed to be tog-
gled on and off from transaction to transaction. Once
an FPGA application determines that it wants to apply
a target abort to any master that accesses it, it would
assert the fpga_tabort signal high. All future target
accesses will be terminated in an abort. In generating
this signal, keep in mind that this signal needs to be
synchronous to pciclk.
Initiating PCI Target Retries
In contrast to target abort, many applications may
require to assert PCI target retries. In general, this may
be asserted for times when the FPGA application is
temporarily busy and unavailable to service PCI
requests. The interface signal, fpga_tretryn, is used
for this purpose. From the PCI core's point of view, it
needs to know whether to perform a target retry at the
very beginning of a transaction, so it is not possible to
have a transaction started and then assert the
fpga_tretryn signal. The signal fpga_tretryn needs to
be asserted before the transaction begins, and it was
not designed to be toggled on and off from transaction
to transaction. Once an FPGA application determines
that it wants to apply a target retry to any master that
accesses it, it would assert the fpga_tretryn signal
low. All future target accesses will be terminated in a
retry (disconnect without data). On the FPGA applica-
tion side, no activity will occur. In generating this signal,
keep in mind that this signal needs to be synchronous
to pciclk.
Lucent Technologies Inc.
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Lucent Technologies Inc.