OR3LP26B Datasheet, PDF (146/184 Pages) Agere Systems – Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface

ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Timing Characteristics (continued)
Table 64. OR3LP26B FPGA Side Interface Clock to Output Delays, fclk Synchronous Signals
OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.
Description (TI = 85 °C, VDD = min, VDD2 = min)
Min
Max
Unit
fpga_msyserror
—
3.779
ns
pci_mcfg_stat
—
4.404
ns
ma_fulln
—
4.314
ns
mstatecntr[2:0]
—
5.796
ns
m_ready
—
4.758
ns
mw_fulln
—
4.348
ns
mw_afulln
—
3.734
ns
datatofpga[63:0] (dual-port mode)
—
8.679
ns
datatofpgax[7:0] (dual-port mode)
—
7.974
ns
mrdata[35:0] (quad-port mode)
—
8.479
ns
twdata[35:0] (quad-port mode)
—
6.867
ns
mr_emptyn
—
3.840
ns
mr_aemptyn
—
3.684
ns
mrlastcycn
—
7.536
ns
disctimerexpn
—
3.436
ns
pci_tcfg_stat
—
3.777
ns
treqn
—
4.932
ns
t_ready
—
4.817
ns
tstatecntr[2:0]
—
4.355
ns
tw_emptyn
—
3.893
ns
tw_aemptyn
—
3.759
ns
twlastcycn
—
7.557
ns
tr_fulln
—
4.358
ns
tr_afulln
—
3.915
ns
trlastcycn
—
5.533
ns
Note: The clock to out parameters are measured from the FCLK1 and FCLK2 clock input pins on the FPGA side, excluding the interbufs, which
traverse the ASIC/FPGA boundary. The ORCA Foundry Static Analysis Tool, Trace, accounts for clock skew and interbuf delays on the
clock and data paths.
146
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