UT7C138 Datasheet, PDF (15/21 Pages) Aeroflex Circuit Technology – 4Kx8/9 Radiation-Hardened Dual-Port Static RAM with Busy Flag

Left Address Valid First:
Address _L
Address_R
BUSY_R
t_{RC or} t_WC
ADDRESS MATCH
t_PS
ADDRESS MISMATCH
t_BLA
t_BZA
Right Address Valid First:
Address_R
Address_L
BUSY_L
t_{RC or} t_WC
ADDRESS MATCH
t_PS
ADDRESS MISMATCH
t_{B L A}
t_BZA
Assumptions:
1. If t_PS is violated, the BUSY signal will be asserted on
one side or the other, but there is no guarantee on which
side BUSY will be asserted.
Figure 5d. BUSY Timing Diagram No. 2 (Address Arbitration)
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