UT7C138 Datasheet, PDF (14/21 Pages) Aeroflex Circuit Technology – 4Kx8/9 Radiation-Hardened Dual-Port Static RAM with Busy Flag

CE _L Valid First:
Address_L,R
CE_L
CE_R
BUSY_R
ADDRESS MATCH
t_PS
t_{B L C}
t_BZC
CE _R Valid First:
Address_L,R
CE_R
CE_L
BUSY_L
ADDRESS MATCH
t_PS
t_BLC
t_BZC
Assumptions:
1. If t_PS is violated, the BUSY signal will be asserted on
one side or the other, but there is no guarantee on which
side BUSY will be asserted.
Figure 5c. BUSY Timing Diagram No. 1 (CE Arbitration)
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