UT7C138 Datasheet, PDF (12/21 Pages) Aeroflex Circuit Technology – 4Kx8/9 Radiation-Hardened Dual-Port Static RAM with Busy Flag

AC CHARACTERISTICS BUSY CYCLE ¹
(V_DD = 5.0V±10%)
SYMBOL
PARAMETER
t_BLA
t_BZA
t_{B L C}
t_{B Z C}
t_PS2,3
t_WB
t_WH
t_BDD
BUSY LOW from address match
BUSY HIGH-Z from address mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port set-up for priority
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to data valid
7C138 - 45
7C139 - 45
MIN MAX
25
25
25
25
5
0
40
45
7C138 - 55
7C139 - 55
MIN MAX
30
30
30
30
5
0
50
55
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1 . Test conditions assume signal transition time of 5ns or less, timing reference levels of V _DD /2, input pulse levels of 0.5V to V_DD-0.5V, and output
loading of the specified I_{O L}/I_OH and 50-pF load capacitance.
2. Violation of t _PS (with addresses matching) results in at least one of the two busy output signals asserting, only one port remains busy.
3. When violating t_PS, the busy signal asserts on one port or the other; there is no guarantee on which port the busy signal asserts.
12