CT1775 Datasheet, PDF (11/14 Pages) Aeroflex Circuit Technology – CT1775 Universal MacAir/1553 Dumb RTU Hybrid

PIN
#
NAME
39 D13
40 D11
41 D9
42 D7
43 D5
44 D3
45 D1
46 LOAD DATA 2
47 +5V
48 +12V
49 RX DATA IN
50 RX STROBE
51 TX DATA OUT
52 CASE
53 DATA SELECT 2
54 DATA SELECT 1
55 ENA PAR CHECK
56 D14
57 D12
58 D10
59 D8
60 D6
61 D4
62 D2
63 D0
64 LOAD DATA 1
65 GND
PIN FUNCTION AND LOADING TABLE (con’t)
I_IH I_IL I_OH I_OL
(µA) (mA) (mA) (mA)
DESCRIPTION
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.4
LOW on this input causes the data of the D0 through D7
outputs of the first rank transmit register to be loaded into
the second rank transmit register. A HIGH locks out the
second rank register inputs.
+5V power supply input.
+12Vpower supply input.
Inverted receiver input.
40 -1.6
A LOW on this input disables the receiver output.
Transmitter output.
Case connection.
20 -0.4
A LOW on this input causes the output of the second rank
receiver register to appear on D0 through D7 of the parallel
tri-state I/O.
20 -0.4
A LOW on this input causes the output of the second rank
receiver register to appear on D8 through D15 of the
parallel tri-state I/O.
20 -0.4
A LOW on this input enables the function of ODD
PARITY.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 LSB of 16 bit parallel tri-state I/O.
20 -0.4
A LOW on this input causes the data of the D8 through
D15 outputs of the first rank transmit register to be loaded
into the second rank transmit register. A HIGH locks out
the second rank register inputs.
Power supply and logic retum
SCDCT1775 Rev B
11