ADV7390_15 Datasheet, PDF (95/108 Pages) Analog Devices – Low Power, Chip Scale, 10-Bit SD/HD Video Encoder

Data Sheet
Table 77. 16-Bit 525i RGB In, CVBS/Y-C Out
Subaddress Setting Description
0x17
0x02 Software reset.
0x00
0x1C All DACs enabled. PLL enabled (16×).
0x01
0x00 SD input mode.
0x80
0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xCB Pixel data valid. CVBS/Y-C (S-Video) out.
SSAF PrPb filter enabled. Active video
edge control enabled. Pedestal enabled.
0x87
0x80 RGB input enabled.
0x88
0x10 16-bit RGB input enabled.
0x8A
0x0C Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 78. 16-Bit 525i RGB In, RGB Out
Subaddress Setting Description
0x17
0x02 Software reset.
0x00
0x1C All DACs enabled. PLL enabled (16×).
0x01
0x00 SD input mode.
0x02
0x10 RGB output enabled. RGB output sync
enabled.
0x80
0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9 Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
0x87
0x80 RGB input enabled.
0x88
0x10 16-bit RGB input enabled.
0x8A
0x0C Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 79. 8-Bit NTSC Square Pixel YCrCb In (EAV/SAV),
CVBS/Y-C Out
Subaddress Setting Description
0x17
0x02 Software reset
0x00
0x1C All DACs enabled. PLL enabled (16×).
0x10 WLCSP required.
0x01
0x00 SD input mode.
0x80
0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xDB Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled. Square pixel mode enabled.
0x8C
0x8D
0x8E
0x8F
0x55
0x55
0x55
0x25
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in NTSC square pixel mode (24.5454
MHz input clock).
ADV7390/ADV7391/ADV7392/ADV7393
Table 80. 16-Bit NTSC Square Pixel RGB In, CVBS/Y-C Out
Subaddress Setting Description
0x17
0x02 Software reset.
0x00
0x1C All DACs enabled. PLL enabled (16×).
0x01
0x00 SD input mode.
0x80
0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xDB Pixel data valid. CVBS/Y-C (S-Video) out.
SSAF PrPb filter enabled. Active video
edge control enabled. Pedestal
enabled. Square pixel mode enabled.
0x87
0x80 RGB input enabled.
0x88
0x10 16-bit RGB input enabled.
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
0x8C
0x8D
0x8E
0x8F
0x55
0x55
0x55
0x25
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in NTSC square pixel mode (24.5454
MHz input clock).
Table 81. 8-Bit 625i YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17
0x02 Software reset.
0x00
0x1C All DACs enabled. PLL enabled (16×).
0x01
0x00 SD input mode.
0x80
0x11 PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x82
0xC1 Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled.
Table 82. 8-Bit 625i YCrCb In (EAV/SAV), CVBS/Y-C Out
Subaddress Setting Description
0x17
0x02 Software reset.
0x00
0x1C All DACs enabled. PLL enabled (16×).
0x10 WLCSP required.
0x01
0x00 SD input mode.
0x80
0x11 PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x82
0xC3 Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled.
0x8C
0x8D
0x8E
0xCB
0x8A
0x09
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in PAL mode (27 MHz input clock).
0x8F
0x2A
Rev. H | Page 95 of 108