ADV7390_15 Datasheet, PDF (15/108 Pages) Analog Devices – Low Power, Chip Scale, 10-Bit SD/HD Video Encoder

Data Sheet
ADV7390/ADV7391/ADV7392/ADV7393
Y OUTPUT
b
HSYNC
VSYNC
PIXEL PORT
Y0 Y1 Y2 Y3
PIXEL PORT*
Cb0 Cr0 Cb2 Cr2
a
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
Figure 12. ED-SDR, 16-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Y OUTPUT
b
HSYNC
VSYNC
PIXEL PORT
Cb0 Y0 Cr0 Y1
a
a(MIN) = 244 CLOCK CYCLES FOR 525p.
a(MIN) = 264 CLOCK CYCLES FOR 625p.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
Figure 13. ED-DDR, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Rev. H | Page 15 of 108