ADV7390_15 Datasheet, PDF (52/108 Pages) Analog Devices – Low Power, Chip Scale, 10-Bit SD/HD Video Encoder

ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
SD VCR FF/RW SYNC
Subaddress 0x82, Bit 5
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for non-
standard input video, that is, in fast forward or rewind modes.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/fields is reached. In rewind mode, this sync
signal usually occurs after the total number of lines/fields is
reached. Conventionally, this means that the output video has
corrupted field signals because one signal is generated by the
incoming video and another is generated when the internal
line/field counters reach the end of a field.
When the VCR FF/RW sync control is enabled (Subaddress 0x82,
Bit 5), the line/field counters are updated according to the
incoming VSYNC signal and when the analog output matches
the incoming VSYNC signal. This control is available in all
slave-timing modes except Slave Mode 0.
VERTICAL BLANKING INTERVAL
Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4
The ADV739x is able to accept input data that contains vertical
blanking interval (VBI) data (such as CGMS, WSS, VITS) in
SD, ED, and HD modes.
If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD; Subaddress
0x83, Bit 4 for SD), VBI data is not present at the output and the
entire VBI is blanked. These control bits are valid in all master
and slave timing modes.
For the SMPTE 293M (525p) standard, VBI data can be inserted
on Line 13 to Line 42 of each frame or on Line 6 to Line 43 for
the ITU-R BT.1358 (625p) standard. VBI data can be present on
Line 10 to Line 20 for NTSC and on Line 7 to Line 22 for PAL.
In SD Timing Mode 0 (slave option), if VBI is enabled, the
blanking bit in the EAV/SAV code is overwritten. It is possible
to use VBI in this timing mode as well.
If CGMS is enabled and VBI is disabled, the CGMS data is,
nevertheless, available at the output.
SD SUBCARRIER FREQUENCY CONTROL
Subaddress 0x8C to Subaddress 0x8F
The ADV739x is able to generate the color subcarrier used in
CVBS and S-Video (Y-C) outputs from the input pixel clock.
Four 8-bit registers are used to set up the subcarrier frequency.
The value of these registers is calculated using the following
equation:
Subcarrier Frequency Register =
Number of subcarrier periods in one video line _{× 232}
Number of 27 MHz clock cycles in one video line
Subcarrier Register Value = _ ^227.5 _ × 2³² = 569408543
 1716 
where:
Subcarrier Register Value = 569408543d = 0×21F07C1F
SD FSC Register 0: 0x1F
SD FSC Register 1: 0x7C
SD FSC Register 2: 0xF0
SD FSC Register 3: 0x21
Programming the FSC
The subcarrier frequency register value is divided into four FSC
registers as shown in the previous example. The four subcarrier
frequency registers must be updated sequentially, starting with
Subcarrier Frequency Register 0 and ending with Subcarrier
Frequency Register 3. The subcarrier frequency updates only
after the last subcarrier frequency register byte is received by
the ADV739x. The SD input standard autodetection feature
must be disabled.
Typical FSC Values
Table 41 outlines the values that should be written to the
subcarrier frequency registers for NTSC and PAL B/D/G/H/I.
Table 41. Typical FSC Values
Subaddress Description
0x8C
FSC0
0x8D
FSC1
0x8E
FSC2
0x8F
FSC3
NTSC
0x1F
0x7C
0xF0
0x21
PAL B/D/G/H/I
0xCB
0x8A
0x09
0x2A
SD NONINTERLACED MODE
Subaddress 0x88, Bit 1
The ADV739x supports an SD noninterlaced mode. Using this
mode, progressive inputs at twice the frame rate of NTSC and
PAL (240p/59.94 Hz and 288p/50 Hz, respectively) can be input
into the ADV739x. The SD noninterlaced mode can be enabled
using Subaddress 0x88, Bit 1.
A 27 MHz clock signal must be provided on the CLKIN pin.
Embedded EAV/SAV timing codes or external horizontal and
vertical synchronization signals provided on the HSYNC
and VSYNC pins can be used to synchronize the input pixel
data.
All input configurations, output configurations, and features
available in NTSC and PAL modes are available in SD noninter-
laced mode. For 240p/59.94 Hz input, the ADV739x should be
configured for NTSC operation and Subaddress 0x88, Bit 1
should be set to 1.
For 288p/50 Hz input, the ADV739x should be configured for
PAL operation and Subaddress 0x88, Bit 1 should be set to 1.
where the sum is rounded to the nearest integer.
For example, in NTSC mode:
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