AD9920ABBCZ Datasheet, PDF (92/112 Pages) Analog Devices – 12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator

AD9920A
SERIAL INTERFACE ³
(FROM ASIC/DSP)
HORIZONTAL SYNC IN/OUT
VERTICAL SYNC IN/OUT
EXTERNAL RESET IN
(TIE TO IOVDD IF RESET IS NOT USED)
DCLK OUTPUT
12
DATA OUTPUTS
6 _{GENERAL-PURPOSE OUTPUTS}
NOTE: ONE GPO IS NEEDED TO DRIVE VDR_EN (PIN B11)
OPTIONAL CLOCK OSCILLATOR OUTPUT
(FOR CRYSTAL APPLICATION)
MASTER CLOCK INPUT (3V LOGIC)
0.1µF
0.1µF
0.1µF
ANALOG OUTPUT FROM CCD
RG TO CCD
HL TO CCD
H7, H8 TO CCD
D8 _A5
D7
D6
A6
D5
D4
D3
D2
B6
B7
A7
A8
C7
D1
(LSB) D0
VDR_EN
C6
B9
B11
GPO OUTPUT
GPO OUTPUT
(OR GND, IF NOT USED)
ANALOG CONTROL INPUT
(OR GND, IF NOT USED)
+3V
SRSW
SRCTL
C9
C2
LEGEN _J6
CCDGND _K7
AVSS _J7
AVSS _K8
NC _A1
NC
NC
A11
L1
NC _L11
NC _B8
NC _B10
NC _J10
AD9920A
NOT DRAWN TO SCALE
H2 ^H6
H1 ^H5
F2 ^H4
F1 ^H3
D2
D1
H2
H1
A9 ^DVSS
K4
K3
TCVSS
RGVSS
E2 ^HVSS1
G2 ^HVSS2
J2 ^HVSS2
G11 ^IOVSS
B2 ^DRVSS/LDOVSS
C10 ^VDVSS
H5, H6 TO CCD
H3, H4 TO CCD
H1, H2 TO CCD
L5 ^CLIVDD
B1 ^LDOIN
C1 ^LDOOUT
0.1µF
0.1µF
+3V CLI SUPPLY
+3V LDO INPUT
+1.8V LDO OUT TO
AVDD, TCVDD, DVDD
A2 ^DRVDD
H11 ^IOVDD
A10
K6
DVDD
TCVDD
L6 ^AVDD
0.1µF
0.1µF
0.1µF
+3V SUPPLY
0.1µF
+1.8V LDO OUT
0.1µF
L3 ^RGVDD
E1 ^HVDD1
G1 ^HVDD2
J1 ^HVDD2
+3V H, RG SUPPLY
0.1µF 0.1µF _4.7µF
6.3V
0.1µF
25V
1.0µF
25V
0.1uF
0.1µF
10V
4.7µF
10V
19
VERTICAL OUTPUT (TO CCD)
SUBCK OUTPUT (TO CCD)
XSUBCNT INPUT (FROM GPO OR TIE TO +3V)
Figure 112. Typical 3 V Circuit Configuration in 19-Channel Mode
VH SUPPLY
VL SUPPLY
+3V SUPPLY
Rev. B | Page 92 of 112