AD9920ABBCZ Datasheet, PDF (21/112 Pages) Analog Devices – 12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator

POSITION
P[0]
CLI
RGr[0]
RG
H1r[0]
H1
H2
P[16]
P[32]
RGf[16]
t_SHDINH
H1f[32]
AD9920A
P[48]
P[64] = P[0]
t_SHDINH
t_S2
t_S1
CCD
SIGNAL
SHP
SHD
SHDLOC[0]
SHPLOC[32]
t_SHPINH
50
62
DOUTPHASEP
1
12
t_DOUTINH
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD.
TYPICAL POSITIONS FOR EACH SIGNAL ARE SHOWN. HCLK MODE 1 IS SHOWN.
2. CERTAIN POSITIONS SHOULD BE AVOIDED FOR EACH SIGNAL, SHOWN ABOVE AS INHIBIT REGIONS.
3. IF A SETTING IN THE INHIBIT REGION IS USED, AN UNSTABLE PIXEL SHIFT CAN OCCUR IN THE HBLK LOCATION OR AFE PIPELINE.
4. THE t_SHPINH AREA FROM 50 TO 62 ONLY APPLIES IN SLAVE MODE.
5. THE t_SHDINH AREA WILL APPLY TO EITHER H1 RISING OR FALLING EDGE, DEPENDING ON THE VALUE OF THE
H1HBLK MASKING POLARITY.
6. THE t_SHDINH AREA CAN ALSO BE CHANGED TO A t_SHPINH AREA IF THE H1HBLKRETIME BIT = 1.
Figure 23. High Speed Timing Default Locations
TAP POSITION P[0]
PHASE 1
PHASE 2
P[16]
SHDINH/SHPINH
P[32]
P[48]
SHDINH/SHPINH
P[64] = P[0]
PHASE 3
RG
HL
RGr[0]
HLr[0]
CCD
SIGNAL
SHP
SHD
SHDLOC[0]
RGf[16]
HLf[32]
SHPLOC[32]
SHDINH/SHPINH
t_S1
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD.
TYPICAL POSITIONS FOR EACH SIGNAL ARE SHOWN USING 3-PHASE HBLK MODE.
2. THE RISING EDGE OF EACH HCLK PHASE HAS AN ASSOCIATED SHDINH.
3. WHEN THE HBLK RETIME BITS (0x35 [3:0]) ARE ENABLED, THE INHIBITED AREA BECOMES SHPINH.
4. WHEN THE HBLK MASK LEVEL FOR PHASE 1, 2, OR 3 IS CHANGED TO LOW, THE INHIBIT AREA IS
REFERENCED TO THE HCLK FALLING EDGE, INSTEAD OF THE HCLK RISING EDGE.
Figure 24. High Speed Timing Typical Locations, 3-Phase HCLK Mode
Rev. B | Page 21 of 112