EVAL-AD7707EB Datasheet, PDF (9/16 Pages) Analog Devices – Evaluation Board for the AD7707 3V/5V, +/-10V Input Range, 1mW, 3Channel, 16-Bit, Sigma Delta ADC

EVAL-AD7707EB
The CLKDIV is used to set the internal operating frequency of the AD7707. The user should consult the datasheet for more
information on the use of the CLKDIV bit.
Fig. 7. The Clock Register Screen
The CLK bit is used in conjunction with the Output Update Rate buttons to select the output update rate.
If the AD7707 is being operated with a clock of 4.9152MHz (CLKDIV=1) or 2.4576MHz (CLKDIV=0) then this bit should
be set to a 1 giving a choice of 50Hz, 60Hz, 250Hz or 500Hz as an output update rate.
If the AD7707 is being operated with a clock of 2MHz (CLKDIV=1) or 1MHz (CLKDIV=0) then this bit should be set to
a 0 giving a choice of 20Hz, 25Hz, 100Hz or 200Hz as an output update rate.
The Power-On/Reset status of this register is 05 hex.
Fig. 7. The Calibration Registers Screen
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Rev. 0