ADSP-BF504 Datasheet, PDF (9/80 Pages) Analog Devices – Blackfin Embedded Processor

Preliminary Technical Data
general-purpose interrupt to the IPEND output asserted is three
core clock cycles; however, the latency can be much higher,
depending on the activity within and the state of the processor.
FLASH MEMORY
The ADSP-BF504F and ADSP-BF506F processors include an
on-chip 32M bit (×16, multiple bank, burst) Flash memory. The
features of this memory include:
• Synchronous/asynchronous read
• Synchronous burst read mode: 50 MHz
• Asynchronous/synchronous read mode
• Random access times: 70 ns
• Synchronous burst read suspend
• Memory blocks
• Multiple bank memory array: 4 Mbit banks
• Parameter blocks (top location)
• Dual operations
• Program erase in one bank while read in others
• No delay between read and write operations
• Block locking
• All blocks locked at power-up
• Any combination of blocks can be locked or locked
down
• Security
• 128-bit user programmable OTP cells
• 64-bit unique device number
• Common Flash interface (CFI)
• 100 000 program/erase cycles per block
Flash memory ships from the factory in an erased state except
for block 0 of the parameter bank. Block 0 of the Flash memory
parameter bank ships from the factory in an unknown state. An
erase operation should be performed prior to programming this
block.
DMA CONTROLLERS
The processor has multiple, independent DMA channels that
support automated data transfers with minimal overhead for
the processor core. DMA transfers can occur between the pro-
cessor’s internal memories and any of its DMA-capable
peripherals. Additionally, DMA transfers can be accomplished
between any of the DMA-capable peripherals and external
devices connected to the external memory interface. DMA-
capable peripherals include the SPORTs, SPI ports, UARTs,
RSI, and PPI. Each individual DMA-capable peripheral has at
least one dedicated DMA channel.
The processor DMA controller supports both one-dimensional
(1-D) and two-dimensional (2-D) DMA transfers. DMA trans-
fer initialization can be implemented from registers or from sets
of parameters called descriptor blocks.
ADSP-BF504/F, ADSP-BF506F
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be de-
interleaved on the fly.
Examples of DMA types supported by the processor DMA con-
troller include:
• A single, linear buffer that stops upon completion
• A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
• 1-D or 2-D DMA using a linked list of descriptors
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels, which are provided for transfers
between the various memories of the processor system with
minimal processor intervention. Memory DMA transfers can be
controlled by a very flexible descriptor-based methodology or
by a standard register-based autobuffer mechanism.
WATCHDOG TIMER
The processor includes a 32-bit timer that can be used to imple-
ment a software watchdog function. A software watchdog can
improve system availability by forcing the processor to a known
state through generation of a core and system reset, non-
maskable interrupt (NMI), or general-purpose interrupt, if the
timer expires before being reset by software. The programmer
initializes the count value of the timer, enables the appropriate
interrupt, then enables the timer. Thereafter, the software must
reload the counter before it counts to zero from the pro-
grammed value. This protects the system from remaining in an
unknown state where software, which would normally reset the
timer, has stopped running due to an external noise condition
or software error.
If configured to generate a reset, the watchdog timer resets both
the core and the processor peripherals. After a reset, software
can determine whether the watchdog was the source of the
hardware reset by interrogating a status bit in the watchdog
timer control register.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of f_SCLK.
TIMERS
There are nine general-purpose programmable timer units in
the processors. Eight timers have an external pin that can be
configured either as a pulse width modulator (PWM) or timer
output, as an input to clock the timer, or as a mechanism for
measuring pulse widths and periods of external events. These
timers can be synchronized: to an external clock input to the
several other associated PF pins, to an external clock input to
the PPI_CLK input pin, or to the internal SCLK.
Rev. PrC | Page 9 of 80 | January 2010