ADSP-BF504 Datasheet, PDF (65/80 Pages) Analog Devices – Blackfin Embedded Processor

Preliminary Technical Data
ADSP-BF504/F, ADSP-BF506F
GND
2 × V_REF p–p
220Ÿ
440Ÿ
V+
27Ÿ
220kŸ
A
20kŸ
V–
220Ÿ
220Ÿ
V+
27Ÿ
V–
10kŸ
3.75V
2.5V
1.25V
V_IN+
ADC¹
3.75V
2.5V
1.25V
V_REF
V_IN– (D_CAPA/D_CAPB)
0.47μF
1_{ADDITIONAL PINS OMITTED FOR CLARITY.}
Figure 79. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal
into a Differential Unipolar Signal
to make use of the full dynamic range of the part. A dc input is
applied to the V_IN– pin. The voltage applied to this input pro-
vides an offset from ground or a pseudo ground for the V_IN+
input. The benefit of pseudo differential inputs is that they sepa-
rate the analog input signal ground from the ADC’s ground
allowing dc common-mode voltages to be cancelled.
The typical voltage range for the V_IN– pin, while in pseudo dif-
ferential mode, is shown in Figure 80 (V_IN– Input Voltage Range
vs. V_REF in Pseudo Differential Mode with V_DD = 3 V) and
Figure 81 (V_IN– Input Voltage Range vs. V_REF in Pseudo Differ-
ential Mode with V_DD = 5 V). Figure 82 (Pseudo Differential
Mode Connection Diagram) shows a connection diagram for
pseudo differential mode.
1.0
T_A = 25°C
0.8
0.6
0.4
0.2
0
–0.2
–0.4
0
0.5
1.0
1.5
2.0
2.5
3.0
V_REF (V)
Figure 80. V_IN- Input Voltage Range vs. V_REF in
Pseudo Differential Mode with V_DD = 3 V
2.5
T_A = 25°C
2.0
1.5
1.0
0.5
0
–0.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V_REF (V)
Figure 81. V_IN– Input Voltage Range vs. V_REF in
Pseudo Differential Mode with V_DD = 5 V
V_REF
p–p
ADC¹
V_IN+
DC INPUT
VOLTAGE
V_IN–
V_{REF (}D_CAPA/D_CAPB)
0.47μF
1_{ADDITIONAL PINS OMITTED FOR CLARITY.}
Figure 82. Pseudo Differential Mode Connection Diagram
Analog Input Selection
The analog inputs of the ADC can be configured as single-
ended or true differential via the SGL/DIFF logic pin, as shown
in Figure 83 (Selecting Differential or Single-Ended Configura-
tion). If this pin is tied to a logic low, the analog input channels
to each on-chip ADC are set up as three true differential pairs. If
this pin is at logic high, the analog input channels to each on-
chip ADC are set up as six single-ended analog inputs. The
required logic level on this pin needs to be established prior to
the acquisition time and remain unchanged during the conver-
sion time until the track-and-hold has returned to track. The
track-and-hold returns to track on the 13^th rising edge of
ADSCLK after the CS falling edge (see Figure 93 (Serial Inter-
face Timing Diagram)). If the level on this pin is changed, it will
be recognized by the ADC; therefore, it is necessary to keep the
same logic level during acquisition and conversion to avoid cor-
rupting the conversion in progress.
For example, in Figure 83 (Selecting Differential or Single-
Ended Configuration) the SGL/DIFF pin is set at logic high for
the duration of both the acquisition and conversion times so the
analog inputs are configured as single ended for that conversion
(Sampling Point A). The logic level of the SGL/DIFF changed to
low after the track-and-hold returned to track and prior to the
Rev. PrC | Page 65 of 80 | January 2010