ADSP-BF504 Datasheet, PDF (63/80 Pages) Analog Devices – Blackfin Embedded Processor

Preliminary Technical Data
ADSP-BF504/F, ADSP-BF506F
–60
F_SAMPLE = 1.5MSPS
V_DD = 3V
–65 ^{RANGE = 0V TO VREF}
R_SOURCE = 0Ÿ
–70
–75
R_SOURCE = 300Ÿ
R_SOURCE = 100Ÿ
–80
R_SOURCE = 47Ÿ
–85
–90
0
R_SOURCE = 10Ÿ
100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (kHz)
Figure 72. THD vs. Analog Input Frequency for
Various Source Impedances, Differential Mode
–50
F_SAMPLE = 1.5MSPS/2MSPS
V_DD = 3V/5V
–55 RANGE = 0 TO V_REF
–60
–65
V_DD = 3V
SINGLE-ENDED MODE
–70
V_DD = 3V
DIFFERENTIAL MODE
–75
–80
–85
–90
0
V_DD = 5V
SINGLE-ENDED MODE
V_DD = 5V
DIFFERENTIAL MODE
100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (kHz)
Figure 73. THD vs. Analog Input Frequency for Various Supply Voltages
Analog Inputs
The ADC has a total of 12 analog inputs. Each on-board ADC
has six analog inputs that can be configured as six single-ended
channels, three pseudo differential channels, or three fully dif-
ferential channels. These may be selected as described in the
Analog Input Selection section.
Single-Ended Mode
The ADC can have a total of 12 single-ended analog input chan-
nels. In applications where the signal source has high
impedance, it is recommended to buffer the analog input
before applying it to the ADC. The analog input range can be
programmed to be either 0 to V_REF or 0 to 2 × V_REF.
If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias up this sig-
nal to make it correctly formatted for the ADC. Figure 74 shows
a typical connection diagram when operating the ADC in sin-
gle-ended mode.
+1.25V
0V
–1.25V
R
V_IN
3R
R
+2.5V
R
0V
V_{A1 ADC}¹
V_REF
V_B6 ^(DCAP^A/DCAP^B)
0.47μF
1_{ADDITIONAL PINS OMITTED FOR CLARITY.}
Figure 74. Single-Ended Mode Connection Diagram
Differential Mode
The ADC can have a total of six differential analog input pairs.
Differential signals have some benefits over single-ended sig-
nals, including noise immunity based on the device’s common-
mode rejection and improvements in distortion performance.
Figure 75 (Differential Input Definition) defines the fully differ-
ential analog input of the ADC.
COMMON
MODE
VOLTAGE
V_REF p-p
V_REF p-p
V_IN+
ADC¹
V_IN–
1_{ADDITIONAL PINS OMITTED FOR CLARITY.}
Figure 75. Differential Input Definition
The amplitude of the differential signal is the difference between
the signals applied to the V_IN+ and V_IN– pins in each differential
pair (V_IN+ V_IN–). V_IN+ and V_IN– should be simultaneously driven
by two signals each of amplitude V_REF (or 2 × V_REF, depending
on the range chosen) that are 180° out of phase. The amplitude
of the differential signal is, therefore (assuming the 0 to V_REF
range is selected) –V_REF to +V_REF peak-to-peak (2 × V_REF),
regardless of the common mode (CM).
The common mode is the average of the two signals
(V_IN+ + V_IN–)/2
and is, therefore, the voltage on which the two inputs are
centered.
This results in the span of each input being CM ± V_REF/2. This
voltage has to be set up externally and its range varies with the
reference value, V_REF. As the value of V_REF increases, the com-
mon-mode range decreases. When driving the inputs with an
amplifier, the actual common-mode range is determined by the
amplifier’s output voltage swing.
Figure 76 (Input Common-Mode Range vs. VREF (0 to VREF
Range, VDD = 5 V)) and Figure 77 (Input Common-Mode
Range vs. VREF (2 × VREF Range, VDD = 5 V)) show how the
common-mode range typically varies with V_REF for a 5 V power
Rev. PrC | Page 63 of 80 | January 2010