AD9786 Datasheet, PDF (9/60 Pages) Analog Devices – 16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2×/4×/8× Interpolation and Signal Processing

ANALOG
Table 6. Analog Pin Function Descriptions
Pin No.
Name
59
REFIO
60
FSADJ
70, 71
IOUTB, IOUTA
61
DNC
62, 79
ADVDD
63, 78
ADGND
64, 77
ACVDD
65, 76
ACGND
66, 75
AVDD2
67, 74
AGND2
68, 73
AVDD1
69, 72
AGND1
80
DNC
Direction
A
A
A
Description
Reference.
Full-Scale Adjust.
Differential DAC Output Currents.
Do Not Connect.
Analog Domain Digital Content 2.5 V.
Analog Domain Digital Content 0 V.
Analog Domain Clock Content 2.5 V.
Analog Domain Clock Content 0 V.
Analog Domain Clock Switching 3.3 V.
Analog Domain Switching 0 V.
Analog Domain Quiet 3.3 V.
Analog Domain Quiet 0 V.
Do Not Connect.
AD9786
DATA
Table 7. Data Pin Function Descriptions
Pin No.
Name
Direction
10–15, 18–24, P1B15–P1B0
I
27–29
32
IQSEL/P2B15
I
33
ONEPORTCLK/P2B14 I/O
34, 37-43,
P2B13-P2B0
I
46–51
30
DRVDD
9, 17, 26,
36, 44, 52
DVDD
8, 16, 25,
35, 45, 53
DGND
Description
Input Data Port One.
ONEPORT
02h[6]
Mode
0
Latched data routed for I channel processing.
1
Latched data demultiplexed by IQSEL and routed for interleaved
I/Q processing.
ONEPORT
IQPOL IQSEL/
02h[6]
02h[1] P2B15 Mode (IQPOL = 0)
0
X
X
Latched data routed to Q channel Bit 15 (MSB)
processing.
1
0
0
Latched data on Data Port One routed to Q
channel processing.
1
0
1
Latched data on Data Port One routed to I
channel processing.
1
1
0
Latched data on Data Port One routed to I
channel processing.
1
1
1
Latched data on Data Port One routed to Q
channel processing.
ONEPORT
02h[6]
0
Latched data routed for Q channel Bit 14 processing.
1
Pin configured for output of clock at twice the channel data route.
Input Data Port Two Bits 13–0.
Digital Output Pin Supply, 2.5 V or 3.3 V.
Digital Domain 2.5 V.
Digital Domain 0 V.
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